A population coding hardware architecture for spiking neural networks applications

Abstract : Recently, Spiking Neural Networks (SNNs) have obtained the interest of Machine Learning researchers due to the rich dynamics shown by these information processing models. One of the most important problems that must be addressed for implementing efficient SNNs is the information encoding. In this paper, an implementation of a high-performance hardware architecture for population information coding based on Gaussian Receptive Fields (GRFs) is proposed. This architecture can be useful for data classifying and clustering applications, because this coding scheme has been used in the past, and an efficient mapping of this technique in hardware can improve the actual performance of these applications. The GRFs information coding can be efficiently implemented on FPGA technology, because it contains several operations that can be computed in parallel like the exponential function. The proposed hardware architecture was implemented, tested and validated with several random datasets. The proposed hardware core is the first step for implementing successfully classifiers like SpikeProp algorithm. Synthesis and timing results for the proposed hardware architecture are presented.
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Communication dans un congrès
IEEE Southern Conference on Programmable Logic - SPL 2009, Apr 2009, Sao Paulo, Brazil. 2009
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https://hal.inria.fr/inria-00434447
Contributeur : Bernard Girau <>
Soumis le : lundi 23 novembre 2009 - 12:26:08
Dernière modification le : jeudi 11 janvier 2018 - 06:19:48

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  • HAL Id : inria-00434447, version 1

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Marco Nuno-Maganda, Miguel Arias-Estrada, César Torres-Huitzil, Bernard Girau. A population coding hardware architecture for spiking neural networks applications. IEEE Southern Conference on Programmable Logic - SPL 2009, Apr 2009, Sao Paulo, Brazil. 2009. 〈inria-00434447〉

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