]. A. Appel and L. George, Optimal spilling for CISC machines with few registers, ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI'01), pp.243-253

T. Ball and J. R. Larus, Branch prediction for free, ACM SIGPLAN Notices, vol.28, issue.6, pp.300-313, 1993.
DOI : 10.1145/173262.155119

B. Boissinot, A. Darte, B. Dupont-de-dinechin, C. Guillon, and F. Rastello, Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency, 2009 International Symposium on Code Generation and Optimization, 2009.
DOI : 10.1109/CGO.2009.19
URL : https://hal.archives-ouvertes.fr/inria-00349925

F. Bouchez, A. Darte, C. Guillon, and F. Rastello, Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How, 19th International Workshop on Languages and Compilers for Parallel Computing (LCPC'06), 2006.
DOI : 10.1007/978-3-540-72521-3_21

P. Brisk, F. Dabiri, J. Macbeth, and M. Sarrafzadeh, Polynomial time graph coloring register allocation, 14th International Workshop on Logic and Synthesis, 2005.

R. Cytron, J. Ferrante, B. Rosen, M. Wegman, and K. Zadeck, Efficiently computing static single assignment form and the control dependence graph, ACM Transactions on Programming Languages and Systems, vol.13, issue.4, pp.451-490, 1991.
DOI : 10.1145/115372.115320

J. Fisher, Trace Scheduling: A Technique for Global Microcode Compaction, IEEE Transactions on Computers, vol.30, issue.7, pp.30478-490, 1981.
DOI : 10.1109/TC.1981.1675827

S. M. Freudenberger, T. R. Gross, and P. G. Lowney, Avoidance and suppression of compensation code in a trace scheduling compiler, ACM Transactions on Programming Languages and Systems, vol.16, issue.4, pp.1156-1214, 1994.
DOI : 10.1145/183432.183446

L. George and A. W. Appel, Iterated register coalescing, ACM Transactions on Programming Languages and Systems, vol.18, issue.3, pp.300-324, 1996.
DOI : 10.1145/229542.229546

S. Hack, Register Allocation for Programs in SSA-Form, 2007.
DOI : 10.1007/11688839_20

S. Hack and G. Goos, Copy coalescing by graph recoloring, ACM SIGPLAN Conference on Programming Language Design and Implementation, pp.227-237, 2008.

S. Hack, D. Grund, and G. Goos, Register Allocation for Programs in SSA-Form, International Conference on Compiler Construction, 2006.
DOI : 10.1007/11688839_20

F. M. Pereira and J. Palsberg, SSA Elimination after Register Allocation, 18th International Conference on Compiler Construction, pp.158-173, 2009.
DOI : 10.1007/978-3-642-00722-4_12

M. Poletto and V. Sarkar, Linear scan register allocation, ACM Transactions on Programming Languages and Systems, vol.21, issue.5, pp.895-913, 1999.
DOI : 10.1145/330249.330250

L. Rideau, B. P. Serpette, and X. Leroy, Tilting at Windmills with Coq: Formal Verification of a Compilation Algorithm for Parallel Moves, Journal of Automated Reasoning, vol.13, issue.12, pp.307-326, 2008.
DOI : 10.1007/s10817-007-9096-8
URL : https://hal.archives-ouvertes.fr/inria-00289709

V. Sarkar and R. Barik, Extended Linear Scan: An Alternate Foundation for Global Register Allocation, International Conference on Compiler Construction, pp.141-155, 2007.
DOI : 10.1007/978-3-540-71229-9_10

V. C. Sreedhar, R. D. Ju, D. M. Gillies, and V. Santhanam, Translating Out of Static Single Assignment Form, 6th International Symposium on Static Analysis, pp.194-210, 1999.
DOI : 10.1007/3-540-48294-6_13

O. Traub, G. H. Holloway, and M. D. Smith, Quality and speed in linear-scan register allocation Optimized interval splitting in a linear scan register allocator, ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI'98) 1st International Conference on Virtual Execution Environments (VEE), pp.142-151, 1998.