Software Pipelining in Nested Loops with Prolog-Epilog Merging

Mohammed Fellahi 1 Albert Cohen 1
1 ALCHEMY - Architectures, Languages and Compilers to Harness the End of Moore Years
LRI - Laboratoire de Recherche en Informatique, UP11 - Université Paris-Sud - Paris 11, CNRS - Centre National de la Recherche Scientifique : UMR8623, Inria Saclay - Ile de France
Abstract : Software pipelining (or modulo scheduling) is a powerful back-end optimization to exploit instruction and vector parallelism. Software pipelining is particularly popular for embedded devices as it improves the computation throughput without increasing the size of the inner loop kernel (unlike loop unrolling), a desirable property to minimize the amount of code in local memories or caches. Unfortunately, common media and signal processing codes exhibit series of low-tripcount inner loops. In this situation, software pipelining is often not an option: it incurs severe fill/drain time overheads and code size expansion due to nested prologs and epilogs. We propose a method to pipeline series of inner loops without increasing the size of the loop nest, apart from an outermost prolog and epilog. Our method achieves significant code size savings and allows pipelining of low-trip-count loops. These benefits come at the cost of additional scheduling constraints, leading to a linear optimization problem to trade memory usage for pipelining opportunities.
Type de document :
Communication dans un congrès
André Seznec and Joel Emer and Mike O'Boyle and Margaret Martonosi and Theo Ungerer. HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. Springer, 2009, 〈10.1007/978-3-540-92990-1_8〉
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https://hal.inria.fr/inria-00445489
Contributeur : Ist Rennes <>
Soumis le : vendredi 8 janvier 2010 - 16:25:03
Dernière modification le : jeudi 11 janvier 2018 - 06:22:13

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Mohammed Fellahi, Albert Cohen. Software Pipelining in Nested Loops with Prolog-Epilog Merging. André Seznec and Joel Emer and Mike O'Boyle and Margaret Martonosi and Theo Ungerer. HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. Springer, 2009, 〈10.1007/978-3-540-92990-1_8〉. 〈inria-00445489〉

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