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IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor

Abstract : This paper proposes an architecture for concurrent scheduling of hard, soft and non real-time threads in embedded systems. It is based on a superscalar in-order processor binary compatible to the Infineon TriCore. The architecture allows a tight static WCET analysis of hard real-time threads. To provide high performance anyway, the absence of speculative elements like branch prediction and out-of-order execution is compensated by multithreading, transforming the processor into an in-order SMT processor. The Priority Controller that manages the scheduling is able (1) to assign fixed portions of time to hard real-time threads, (2) to control the IPC of soft real-time threads and (3) to fairly distribute execution cycles to non real-time threads. It is located within a separate unit outside the pipeline to avoid prolonging the critical path. We evaluate the processor using the EEMBC automotive benchmarks and show that the overlapping of two soft real-time threads can be used to either reduce the clock rate by 23% or to grant each thread 65% of its single-threaded IPC. Even if a hard real-time thread is executed predominantly, the remaining resources can be used by concurrent soft real-time threads which reach a performance of 70% compared to their single-threaded execution.
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https://hal.inria.fr/inria-00445865
Contributor : Ist Rennes <>
Submitted on : Monday, January 11, 2010 - 2:56:27 PM
Last modification on : Saturday, November 24, 2018 - 1:54:08 PM

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Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer. IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor. HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_11⟩. ⟨inria-00445865⟩

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