Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), pp.46-50, 2005. ,
DOI : 10.1109/ISVLSI.2005.52
A design flow for partially reconfigurable hardware, ACM Transactions on Embedded Computing Systems, vol.3, issue.2, pp.257-283, 2004. ,
DOI : 10.1145/993396.993399
A prototype chip of multicontext FPGA with DRAM for virtual hardware, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455), pp.17-18, 2001. ,
DOI : 10.1109/ASPDAC.2001.913267
FPGA architecture extensions for preemptive multitasking and hardware defragmentation, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921), pp.433-436, 2004. ,
DOI : 10.1109/FPT.2004.1393318
Object-Oriented Meta Tools for Reconfigurable Architectures, Proceedings of the SPIE Conference on Modeling, Signal Processing, and Control, pp.69-79, 2000. ,
DOI : 10.1117/12.402529
Decoder-Driven Switching Matrices in Multicontext FPGAs: Area Reduction and Their Effect on Routability, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp.463-466, 1999. ,
A cost-effective context memory structure for dynamically reconfigurable processors, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, pp.1101-1109, 2006. ,
DOI : 10.1109/IPDPS.2006.1639433
Wideband CDMA For Third Generation Mobile Communication, 1998. ,
Energy-efficient NoC for best effort communication, International Conference on Field Programmable Logic and Applications, 2005., pp.197-202, 2005. ,
DOI : 10.1109/FPL.2005.1515722
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.324.4141
DART: a dynamically reconfigurable architecture dealing with future mobile telecommunications constr, Proceedings 16th International Parallel and Distributed Processing Symposium, pp.118-123, 2002. ,
DOI : 10.1109/IPDPS.2002.1016554
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency, EURASIP Journal on Embedded Systems, vol.2008, issue.13, 2008. ,
DOI : 10.1109/35.714616
URL : https://hal.archives-ouvertes.fr/inria-00446682
Virtex series configuration architecture, 2004. ,
Architecture Exploration for a Reconfigurable Architecture Template, IEEE Journal of Design and Test, vol.22, issue.2, pp.90-101, 2005. ,
VPR: a new packing, placement and routing tool for FPGA research, Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), pp.213-222, 1997. ,
DOI : 10.1007/3-540-63465-7_226
Benchmarking Method and Designs Targeting Logic Synthesis for FPGAs, Proceedings of the ACM/SIGDA International Workshop on Logic and Synthesis (IWLS), pp.230-237, 2007. ,