The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design constraints. Many high performance computing platforms are integrating several homogeneous or heterogeneous processing cores on the same die to fit small form factors. Due to design limitations of using expensive cooling solutions, complex chip multiprocessors require an architectural solution to mitigate thermal problems. Many of the proposed systems deploy DVFS to address thermal emergencies, either within an operating system or hardware. These techniques have certain limitations in terms of response lag, scalability, cost or being reactive. In this paper, we present an alternative thermal management system to address these limitations, based on co-designed virtual machines concept. The proposed scheme delivers localized and preemptive response to thermal events, adapts well to multi-core and multi-threading environment, while delivering maximum performance under thermal stress.