Parallel H.264 Decoding on an Embedded Multicore Processor

Arnaldo Azevedo 1 Cor Meenderinck Ben Juurlink 1 Andrei Terechko 2 Jan Hoogerbrugge 2 Mauricio Alvarez 3 Alex Ramirez 3, 4
1 CE - Computer Engineering - Delft University of Technology
2 NXP Semiconductors
3 UPC - Technical University of Catalonia
4 BSC - CNS - Barcelona Supercomputing Center - Centro Nacional de Supercomputacion
Abstract : In previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is based on the observation that inter-frame dependencies have a limited spatial range. The previous results, however, investigate application scalability on an idealized multiprocessor. This work presents an implementation of the 3D-Wave strategy on a multicore architecture composed of NXP TriMedia TM3270 embedded processors. The results show that the parallel H.264 implementation scales very well, achieving a speedup of more than 54 on a 64-core processor. Potential drawbacks of the 3D-Wave strategy are that the memory requirements increase since there can be many frames in flight, and that the latencies of some frames might increase. To address these drawbacks, policies to reduce the number of frames in flight and the frame latency are also presented. The results show that our policies combat memory and latency issues with a negligible effect on the performance scalability.
Type de document :
Communication dans un congrès
André Seznec and Joel Emer and Mike O'Boyle and Margaret Martonosi and Theo Ungerer. HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. Springer, 2009, 〈10.1007/978-3-540-92990-1_29〉
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https://hal.inria.fr/inria-00446428
Contributeur : Ist Rennes <>
Soumis le : mardi 12 janvier 2010 - 16:12:59
Dernière modification le : lundi 29 janvier 2018 - 13:04:01

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Arnaldo Azevedo, Cor Meenderinck, Ben Juurlink, Andrei Terechko, Jan Hoogerbrugge, et al.. Parallel H.264 Decoding on an Embedded Multicore Processor. André Seznec and Joel Emer and Mike O'Boyle and Margaret Martonosi and Theo Ungerer. HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. Springer, 2009, 〈10.1007/978-3-540-92990-1_29〉. 〈inria-00446428〉

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