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A Fault-Tolerant Layer For Dynamically Reconfigurable Multi-Processor System-On-Chip

Hung-Manh Pham 1 Sébastien Pillement 1 Didier Demigny 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Document type :
Conference papers
Complete list of metadatas
https://hal.inria.fr/inria-00446946
Contributor : Sébastien Pillement <>
Submitted on : Wednesday, January 13, 2010 - 5:31:56 PM
Last modification on : Friday, July 10, 2020 - 4:07:54 PM

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  • HAL Id : inria-00446946, version 1

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CNRS | INRIA | IRISA | UNIV-RENNES1 | IRISA-D3 | UR1-UFR-ISTIC | UNIV-RENNES | INSTITUT-TELECOM | INSA-RENNES

Citation

Hung-Manh Pham, Sébastien Pillement, Didier Demigny. A Fault-Tolerant Layer For Dynamically Reconfigurable Multi-Processor System-On-Chip. International Conference on ReConFigurable Computing and FPGAs, ReConFig'09, Dec 2009, Cancun, Mexico. ⟨inria-00446946⟩

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