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A Generic Architecture of CCSDS Low Density Parity Check Decoder for Near-Earth Applications
Abstract : Low Density Parity Check (LDPC) codes have recently been chosen in the CCSDS standard for uses in near-earth applications. The specified code belongs to the class of Quasi-Cyclic LDPC codes which provide very high data rates and high reliability. Even if these codes are suited to high data rate, the complexity of LDPC decoding is a real challenge for hardware engineers. This paper presents a generic architecture for a CCSDS LDPC decoder. This architecture uses the regularity and the parallelism of the code and a genericity based on an optimized storage of the data. Two FPGA implementations are proposed: the first one is low-cost oriented and the second one targets high-speed decoder.
Cited literature [6 references]
https://hal.inria.fr/inria-00449731
Contributor : François Charot <>
Submitted on : Friday, January 22, 2010 - 2:43:56 PM
Last modification on : Friday, July 10, 2020 - 4:13:57 PM
Document(s) archivé(s) le : Thursday, June 17, 2010 - 11:12:22 PM
Contributor : François Charot <>
Submitted on : Friday, January 22, 2010 - 2:43:56 PM
Last modification on : Friday, July 10, 2020 - 4:13:57 PM
Document(s) archivé(s) le : Thursday, June 17, 2010 - 11:12:22 PM
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charot_date09.pdf
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