A Generic Architecture of CCSDS Low Density Parity Check Decoder for Near-Earth Applications

Fabien Demangel 1 Nicolas Fau 1 Nicolas Drabik 1 François Charot 2 Christophe Wolinski 2
1 R-interface
2 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
IRISA-D3 - ARCHITECTURE, Inria Rennes – Bretagne Atlantique
Abstract : Low Density Parity Check (LDPC) codes have recently been chosen in the CCSDS standard for uses in near-earth applications. The specified code belongs to the class of Quasi-Cyclic LDPC codes which provide very high data rates and high reliability. Even if these codes are suited to high data rate, the complexity of LDPC decoding is a real challenge for hardware engineers. This paper presents a generic architecture for a CCSDS LDPC decoder. This architecture uses the regularity and the parallelism of the code and a genericity based on an optimized storage of the data. Two FPGA implementations are proposed: the first one is low-cost oriented and the second one targets high-speed decoder.
Keywords : cyclic codes parity check codes hardware FPGA
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Conference papers
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https://hal.inria.fr/inria-00449731
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Fabien Demangel, Nicolas Fau, Nicolas Drabik, François Charot, Christophe Wolinski. A Generic Architecture of CCSDS Low Density Parity Check Decoder for Near-Earth Applications. Design, Automation & Test in Europe Conference & Exhibition, 2009 (DATE '09), Apr 2009, Nice, France. pp.1242-1245. ⟨inria-00449731⟩

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