Architecture-Driven Synthesis of Reconfigurable Cells

Christophe Wolinski 1 Krzysztof Kuchcinski 2 Erwan Raffin 3 François Charot 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
2 Department of Computer Science [Lund]
3 Thomson Multimedia R&D France
Abstract : In this paper, we present a novel method for merging sets of computational patterns into a reconfigurable cell respecting design constraints and optimizing specific design aspects. Each cell can then be used in a run-time reconfigurable processor extension. Our method uses constraint programming to define the pattern merging problem and therefore can easily include design constraints and optimize different design aspects. Experiments carried out on Media-Bench test suite indicate 50% average reduction of cell area without increasing critical path.
Keywords : ASIP reconfigurable computing scheduling instruction selection constraint programming
Document type :
Conference papers
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https://hal.inria.fr/inria-00449757
Contributor : François Charot <>
Submitted on : Friday, January 22, 2010 - 3:25:18 PM
Last modification on : Friday, November 16, 2018 - 1:40:03 AM
Long-term archiving on: Thursday, June 17, 2010 - 9:14:49 PM

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  • HAL Id : inria-00449757, version 1

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CNRS | INRIA | IRISA | UNIV-RENNES1 | IRISA-D3 | INSTITUT-TELECOM | UR1-UFR-ISTIC | UNIV-RENNES

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Christophe Wolinski, Krzysztof Kuchcinski, Erwan Raffin, François Charot. Architecture-Driven Synthesis of Reconfigurable Cells. 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (DSD 2009), Aug 2009, Patras, Greece. pp.531-538. ⟨inria-00449757⟩

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