A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture

François Charot 1 Christophe Wolinski 1 Nicolas Fau 2 François Hamon 2
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
2 R-interface
Abstract : We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the 802.16e WiMax standard. The proposed design is fully compliant with all the code classes defined by the standard. It has been validated through an implementation on a Xilinx Virtex5 FPGA component. A four or six-module FPGA design yields a throughput ranging from 10 to 30 Mbit/s by means of 20 iterations at a clock frequency of 160 MHz which mostly satisfies communication throughput in the case of the WiMax Mobile communication.
Type de document :
Communication dans un congrès
16th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2008), Apr 2008, Palo Alto, United States. pp.314-315, 2008
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https://hal.inria.fr/inria-00449829
Contributeur : François Charot <>
Soumis le : vendredi 22 janvier 2010 - 17:33:29
Dernière modification le : mercredi 16 mai 2018 - 11:23:26
Document(s) archivé(s) le : vendredi 18 juin 2010 - 01:19:49

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François Charot, Christophe Wolinski, Nicolas Fau, François Hamon. A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture. 16th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2008), Apr 2008, Palo Alto, United States. pp.314-315, 2008. 〈inria-00449829〉

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