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A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture
Abstract : We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the 802.16e WiMax standard. The proposed design is fully compliant with all the code classes defined by the standard. It has been validated through an implementation on a Xilinx Virtex5 FPGA component. A four or six-module FPGA design yields a throughput ranging from 10 to 30 Mbit/s by means of 20 iterations at a clock frequency of 160 MHz which mostly satisfies communication throughput in the case of the WiMax Mobile communication.
https://hal.inria.fr/inria-00449829
Contributor : François Charot <>
Submitted on : Friday, January 22, 2010 - 5:33:29 PM
Last modification on : Friday, July 10, 2020 - 4:14:00 PM
Document(s) archivé(s) le : Friday, June 18, 2010 - 1:19:49 AM
Contributor : François Charot <>
Submitted on : Friday, January 22, 2010 - 5:33:29 PM
Last modification on : Friday, July 10, 2020 - 4:14:00 PM
Document(s) archivé(s) le : Friday, June 18, 2010 - 1:19:49 AM
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charot_fccm08.pdf
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