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A Parallel and Modular Architecture for 802.16e LDPC Codes
Abstract : We propose a parallel and modular architecture well suited to 802.16e WiMax LDPC code decoding. The proposed design is fully compliant with all the code classes defined by the WiMax standard. It has been validated through an implementation on a Xilinx Virtex5 FPGA component. A four or six-module FPGA design yields a throughput ranging from 10 to 30 Mbit/s by means of 20 iterations at a clock frequency of 160 MHz which mostly satisfies communication throughput in the case of the WiMax Mobile communication.
Cited literature [7 references]
https://hal.inria.fr/inria-00449834
Contributor : François Charot <>
Submitted on : Friday, January 22, 2010 - 5:42:19 PM
Last modification on : Friday, July 10, 2020 - 4:00:16 PM
Document(s) archivé(s) le : Friday, June 18, 2010 - 1:19:56 AM
Contributor : François Charot <>
Submitted on : Friday, January 22, 2010 - 5:42:19 PM
Last modification on : Friday, July 10, 2020 - 4:00:16 PM
Document(s) archivé(s) le : Friday, June 18, 2010 - 1:19:56 AM
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charot_dsd08.pdf
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