Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures

Christophe Wolinski 1 Krzysztof Kuchcinski 2 Jürgen Teich 3 Frank Hannig 3
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
IRISA-D3 - ARCHITECTURE, Inria Rennes – Bretagne Atlantique
2 Department of Computer Science [Lund]
3 CS 12 - Department of Computer Science 12, Hardware-Software-Co-Design
Abstract : In this paper, we introduce a constraint programming- based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data between processors. Here, we support also multi-casting data transfers for the first time. The routing found by our method minimizes the area or the reconfiguration time of the communication network, when switching between the execution of these algorithms. In fact, when switching, the communication network reconfiguration can be executed in just a few clock cycles. Moreover the communication network area can be minimized signifiHeidelbergcantly (62% in average).
Document type :
Conference papers
Complete list of metadatas

Cited literature [12 references]  Display  Hide  Download
https://hal.inria.fr/inria-00451667
Contributor : François Charot <>
Submitted on : Friday, January 29, 2010 - 4:11:15 PM
Last modification on : Friday, November 16, 2018 - 1:39:39 AM
Long-term archiving on: Friday, June 18, 2010 - 5:31:40 PM

File

wolinski-fpl08.pdf
Publisher files allowed on an open archive

Identifiers

Collections

CNRS | INRIA | IRISA | UNIV-RENNES1 | IRISA-D3 | INSTITUT-TELECOM | UR1-UFR-ISTIC | UNIV-RENNES

Citation

Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig. Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures. International Conference on Field Programmable Logic and Applications (FPL 2008), Sep 2008, Heidelberg, Germany. pp.391-396, ⟨10.1109/FPL.2008.4629969⟩. ⟨inria-00451667⟩

Export

BibTeX TEI DC DCterms EndNote

Share

Metrics

Record views

391

Files downloads

220

 

 

Contact

archive-ouverte@inria.fr