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Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures
Abstract : In this paper, we introduce a constraint programming- based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data between processors. Here, we support also multi-casting data transfers for the first time. The routing found by our method minimizes the area or the reconfiguration time of the communication network, when switching between the execution of these algorithms. In fact, when switching, the communication network reconfiguration can be executed in just a few clock cycles. Moreover the communication network area can be minimized signifiHeidelbergcantly (62% in average).
Cited literature [12 references]
https://hal.inria.fr/inria-00451667
Contributor : François Charot <>
Submitted on : Friday, January 29, 2010 - 4:11:15 PM
Last modification on : Friday, July 10, 2020 - 4:08:51 PM
Document(s) archivé(s) le : Friday, June 18, 2010 - 5:31:40 PM
Contributor : François Charot <>
Submitted on : Friday, January 29, 2010 - 4:11:15 PM
Last modification on : Friday, July 10, 2020 - 4:08:51 PM
Document(s) archivé(s) le : Friday, June 18, 2010 - 5:31:40 PM
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wolinski-fpl08.pdf
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