Combining flash memory and FPGAs to efficiently implement a massively parallel algorithm for content-based image retrieval

Chikhi Rayan 1 Steven Derrien 2 Noumsi Auguste 2 Patrice Quinton 2
1 SYMBIOSE - Biological systems and models, bioinformatics and sequences
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
2 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : With ever larger and more affordable storage capabilities, individuals and companies can now collect huge amounts of multimedia data, especially images. Searching such databases is still an open problem, known as content-based image retrieval (CBIR). In this paper, we present a hardware architecture based on FPGAs which aims at speeding-up visual CBIR. Our architecture is based on the unique combination of reconfigurable resources and flash memory, allows for a speed-up factor of 45 as compared to existing software solutions.
Type de document :
Article dans une revue
International Journal of Electronics, Taylor & Francis, 2008, 95 (7), pp.621-635(15)
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https://hal.inria.fr/inria-00453946
Contributeur : Steven Derrien <>
Soumis le : samedi 6 février 2010 - 15:15:28
Dernière modification le : mercredi 16 mai 2018 - 11:23:26

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  • HAL Id : inria-00453946, version 1

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Chikhi Rayan, Steven Derrien, Noumsi Auguste, Patrice Quinton. Combining flash memory and FPGAs to efficiently implement a massively parallel algorithm for content-based image retrieval. International Journal of Electronics, Taylor & Francis, 2008, 95 (7), pp.621-635(15). 〈inria-00453946〉

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