Hardware Acceleration of HMMER on FPGAs

Steven Derrien 1 Patrice Quinton 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : We propose a new parallelization scheme for the hmmsearch function of the HMMER software, in order to target FPGA technology. hmmsearch is a very compute intensive software for biological sequence alignment, based on profile hidden Markov models. We derive a flexible, generic, scalable hardware parallel architecture which can accelerate the core of hmmsearch by nearly two orders of magnitude, without modifying the original algorithm of this software. Our derivation is based on the expression of the algorithm as a set of recurrence equations, and we show in a systematic way how a very efficient parallel version of the algorithm can be found by combining scheduling, projection, partitioning, pipelining and precision analysis. We present the performance of the implementation of this parallel algorithm on a FPGA platform.
Type de document :
Article dans une revue
Journal of Signal Processing Systems, Springer, 2010, 58 (1), pp.53-67. 〈10.1007/s11265-008-0262-y〉
Liste complète des métadonnées

https://hal.inria.fr/inria-00453947
Contributeur : Steven Derrien <>
Soumis le : samedi 6 février 2010 - 15:20:46
Dernière modification le : mercredi 11 avril 2018 - 01:57:22

Lien texte intégral

Identifiants

Citation

Steven Derrien, Patrice Quinton. Hardware Acceleration of HMMER on FPGAs. Journal of Signal Processing Systems, Springer, 2010, 58 (1), pp.53-67. 〈10.1007/s11265-008-0262-y〉. 〈inria-00453947〉

Partager

Métriques

Consultations de la notice

202