Graph Constraints in Embedded System Design

Abstract : In this paper, we present application of graph constraints combined with finite domain constraints for embedded system optimization problems. In particular, we present methods for identification and selection of computational patterns as well as application scheduling with these patterns that has direct application in ASIP processor design. In this work we use connected component, (sub)graph isomorphism and clique constraints. Our experimental results show that these methods work for relatively large examples and provide much better results than previous heuristic based approaches.
Type de document :
Communication dans un congrès
Worshop on Combinatorial Optimization for Embedded System Design (COESD 2010), Jun 2010, Bologne, Italy. 2010
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https://hal.inria.fr/inria-00481135
Contributeur : François Charot <>
Soumis le : jeudi 6 mai 2010 - 09:21:35
Dernière modification le : mercredi 16 mai 2018 - 11:23:26

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  • HAL Id : inria-00481135, version 1

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Christophe Wolinski, Krzysztof Kuchcinski, Kevin Martin, Antoine Floch, Erwan Raffin, et al.. Graph Constraints in Embedded System Design. Worshop on Combinatorial Optimization for Embedded System Design (COESD 2010), Jun 2010, Bologne, Italy. 2010. 〈inria-00481135〉

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