Requirements traceability modeling is a key issue in real-time embedded design process. In such systems, requirements are of different nature (software-related, system-related, functional and non functional) and must be traced through a multi level design flow which integrates multiple and heterogeneous models. Validation and Verification (V&V) activities must be performed on models and on the final product to check if they are matching the initial require-ments. Results of a design and of V&V activities must impact the traceability information. We propose the DARWIN4REQ metamodel for requirement traceability based on three indepen-dent flows (requirement model, solution model and V&V model). The DARWIN4REQ metamodel establishes the link between these flows and allows a full traceability of requirements including the heterogeneous models. This paper presents the DARWIN4REQ metamodel and its use in the context of heterogeneous models for requirement modeling, design and V&V. An automotive application illustrates the approach with SYSML, EAST_ADL2 and MARTE for the design and SIMULINK, SyNDEx and TIMESQUARE for V&V activities.