K. Van-berkel, Handshake Circuits: An Asynchronous Architecture for Vlsi Programming, 1994.
DOI : 10.1017/CBO9780511585777

I. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin et al., Handshake protocols for de-synchronization, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings., p.149158, 2004.
DOI : 10.1109/ASYNC.2004.1299296

P. Bomel, É. Martin, and E. Boutillon, Synchronization Processor Synthesis for Latency Insensitive Systems, Design, Automation and Test in Europe, p.896897, 2005.
DOI : 10.1109/DATE.2005.287

URL : https://hal.archives-ouvertes.fr/hal-00077965

J. Boucaron, R. De-simone, and J. Millo, Latency-insensitive design and central repetitive scheduling, Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings., p.175183, 2006.
DOI : 10.1109/MEMCOD.2006.1695923

URL : https://hal.archives-ouvertes.fr/inria-00071374

J. Boucaron, R. De-simone, and J. Millo, Formal methods for scheduling of latency-insensitive designs, EURASIP Journal on Embedded Systems, issue.1, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00784464

J. Boucaron, J. Millo, R. , and S. , Another Glance at Relay Stations in Latency-Insensitive Design, Electronic Notes in Theoretical Computer Science ENTCS 146-2, p.4159, 2006.
DOI : 10.1016/j.entcs.2005.05.035

P. Luca and . Carloni, The role of back-pressure in implementing latency-insensitive systems, Electronic Notes in Theoretical Computer Science ENTCS 146-2, 2006.

P. Luca, K. L. Carloni, A. L. Mcmillan, and . Sangiovanni-vincentelli, Theory of Latency-Insensitive Design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001.

P. Luca, A. L. Carloni, and . Sangiovanni-vincentelli, Coping with latency in soc design, IEEE Micro, vol.22, issue.5, p.2435, 2002.

R. Mario, L. Casu, and . Macchiarulo, A Detailed Implementation of Latency Insensitive Protocols, FMGALS 2003 Proceedings, 2003.

R. Mario, L. Casu, and . Macchiarulo, A New Approach to Latency Insensitive Design, 2004.

J. Cortadella, M. Kishinevsky, and B. Grundmann, Synthesis of synchronous elastic architectures, Proceedings of the 43rd annual conference on Design automation , DAC '06, p.657662, 2006.
DOI : 10.1145/1146909.1147077

C. Svensson, Synchronous Latency Insensitive Design route des Lucioles -BP 93 -06902 Sophia Antipolis Cedex (France) Unité de recherche INRIA Futurs : Parc Club Orsay Université -ZAC des Vignes 4, ASYNC'04, 2004.

I. Unité-de-recherche and . Lorraine, Technopôle de Nancy-Brabois -Campus scientifique 615, rue du Jardin Botanique -BP 101 -54602 Villers-lès-Nancy Cedex (France) Unité de recherche INRIA Rennes : IRISA, Campus universitaire de Beaulieu -35042 Rennes Cedex (France) Unité de recherche INRIA Rhône-Alpes : 655, avenue de l'Europe -38334 Montbonnot Saint-Ismier (France) Unité de recherche INRIA Rocquencourt, Domaine de Voluceau -Rocquencourt -BP 105 -78153 Le Chesnay Cedex

I. De-voluceau-rocquencourt, BP 105 -78153 Le Chesnay Cedex (France) http://www.inria.fr ISSN, pp.249-6399