MARTE based design flow for Partially Reconfigurable Systems-on-Chips

Imran Rafiq Quadri 1, 2, * Alexis Muller 1, 2 Samy Meftali 1, 2 Jean-Luc Dekeyser 1
* Corresponding author
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : Systems-on-Chip (SoCs) are considered an integral solution for designing embedded systems, for targeting complex intensive parallel computation applications. As advances in SoC technology permit integration of increasing number of hardware resources on a single chip, the targeted application domains such as software-defined radio are become increasingly sophisticated. The fallout of this complexity is that the system design, particularly software design, does not evolve at the same pace as that of hardware leading to a significant productivity gap. Adaptivity and reconfigurability are also critical issues for SoCs which must be able to cope with end user environment and requirements.
Document type :
Conference papers
Complete list of metadatas

Cited literature [27 references]  Display  Hide  Download

https://hal.inria.fr/inria-00486846
Contributor : Imran Rafiq Quadri <>
Submitted on : Thursday, May 27, 2010 - 2:29:48 AM
Last modification on : Thursday, February 21, 2019 - 10:52:49 AM
Long-term archiving on : Thursday, September 16, 2010 - 3:54:13 PM

File

vlsisoc09.pdf
Files produced by the author(s)

Identifiers

  • HAL Id : inria-00486846, version 1

Collections

Citation

Imran Rafiq Quadri, Alexis Muller, Samy Meftali, Jean-Luc Dekeyser. MARTE based design flow for Partially Reconfigurable Systems-on-Chips. 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 09), Oct 2009, Florianapolis, Brazil. ⟨inria-00486846⟩

Share

Metrics

Record views

820

Files downloads

339