MARTE based design flow for Partially Reconfigurable Systems-on-Chips

Imran Rafiq Quadri 1, 2, * Alexis Muller 1, 2 Samy Meftali 1, 2 Jean-Luc Dekeyser 1
* Auteur correspondant
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : Systems-on-Chip (SoCs) are considered an integral solution for designing embedded systems, for targeting complex intensive parallel computation applications. As advances in SoC technology permit integration of increasing number of hardware resources on a single chip, the targeted application domains such as software-defined radio are become increasingly sophisticated. The fallout of this complexity is that the system design, particularly software design, does not evolve at the same pace as that of hardware leading to a significant productivity gap. Adaptivity and reconfigurability are also critical issues for SoCs which must be able to cope with end user environment and requirements.
Type de document :
Communication dans un congrès
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 09), Oct 2009, Florianapolis, Brazil. 2009
Liste complète des métadonnées

Littérature citée [27 références]  Voir  Masquer  Télécharger

https://hal.inria.fr/inria-00486846
Contributeur : Imran Rafiq Quadri <>
Soumis le : jeudi 27 mai 2010 - 02:29:48
Dernière modification le : vendredi 30 mars 2018 - 16:08:30
Document(s) archivé(s) le : jeudi 16 septembre 2010 - 15:54:13

Fichier

vlsisoc09.pdf
Fichiers produits par l'(les) auteur(s)

Identifiants

  • HAL Id : inria-00486846, version 1

Collections

Citation

Imran Rafiq Quadri, Alexis Muller, Samy Meftali, Jean-Luc Dekeyser. MARTE based design flow for Partially Reconfigurable Systems-on-Chips. 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 09), Oct 2009, Florianapolis, Brazil. 2009. 〈inria-00486846〉

Partager

Métriques

Consultations de la notice

486

Téléchargements de fichiers

265