F. Maraninchi and Y. Rémond, Mode-automata: About modes and states for reactive systems, European Symposium On Programming. Lisbon (Portugal), 1998.
DOI : 10.1007/BFb0053571

P. Lysaght, B. Blodget, and J. Mason, Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs, 2006 International Conference on Field Programmable Logic and Applications, 2006.
DOI : 10.1109/FPL.2006.311188

T. Mens and P. Van-gorp, A Taxonomy of Model Transformation, Proceedings of the International Workshop on Graph and Model Transformation, pp.125-142, 2005.
DOI : 10.1016/j.entcs.2005.10.021

I. Quadri, S. Meftali, and J. Dekeyser, A model driven design flow for fpgas supporting partial reconfiguration Tentative publication date, International Journal of Reconfigurable Computing, 2009.

A. Koudri, Using MARTE in the MOPCOM SoC/SoPC Co- Methodology, MARTE Workshop at DATE'08, 2008.

F. Berthelot, F. Nouvel, and D. Houzet, A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs, EURASIP Journal on Embedded Systems, vol.49, issue.3, pp.1-18, 2008.
DOI : 10.1155/S1110865704402066

URL : https://hal.archives-ouvertes.fr/hal-00320192

S. Graf, OMEGA: correct development of real time and embedded systems, Software & Systems Modeling, vol.8, issue.2, pp.127-130, 2008.
DOI : 10.1007/s10270-007-0077-5

M. Segarra and F. André, A framework for dynamic adaptation in wireless environments, Proceedings 33rd International Conference on Technology of Object-Oriented Languages and Systems TOOLS 33, pp.336-347, 2000.
DOI : 10.1109/TOOLS.2000.848773

J. Buisson, F. André, and J. Pazat, A Framework for Dynamic Adaptation of Parallel Components, ParCo 2005, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00498836

D. Latella, I. Majzik, and M. Massink, Automatic Verification of a Behavioral Subset of UML Statechart Diagrams Using the SPIN Model- Checker, Formal Aspects Computing, pp.637-664

T. Schäfer, A. Knapp, and S. Merz, Model Checking UML State Machines and Collaborations, CAV Workshop on Software Model Checking, 2001.
DOI : 10.1016/S1571-0661(04)00262-2

B. Nascimento, A partial reconfigurable architecture for controllers based on Petri nets, Proceedings of the 17th symposium on Integrated circuits and system design , SBCCI '04, pp.16-21, 2004.
DOI : 10.1145/1016568.1016581

L. Apvrille, W. Muhammad, R. Ameur-boulifa, S. Coudert, and R. Pacalet, A UML-based Environment for System Design Space Exploration, 2006 13th IEEE International Conference on Electronics, Circuits and Systems, pp.1272-1275, 2006.
DOI : 10.1109/ICECS.2006.379694

URL : https://hal.archives-ouvertes.fr/hal-00525101

P. Sedcole, B. Blodget, J. Anderson, P. Lysaght, and T. Becker, Modular partial reconfiguration in virtex FPGAs, International Conference on Field Programmable Logic and Applications, 2005., pp.211-216, 2005.
DOI : 10.1109/FPL.2005.1515724

J. Becker, M. Huebner, and M. Ullmann, Real-Time Dynamically Run-Time Reconfigurations for Power/Cost-optimized Virtex FPGA Realizations, VLSI'03, 2003.

M. Huebner, C. Schuck, M. Kiihnle, and J. Becker, New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.
DOI : 10.1109/ISVLSI.2006.67

C. Schuck, M. Kuhnle, M. Hubner, and J. Becker, A framework for dynamic 2D placement on FPGAs, 2008 IEEE International Symposium on Parallel and Distributed Processing, 2008.
DOI : 10.1109/IPDPS.2008.4536512

. Xilinx, Early Access Partial Reconfigurable Flow, 2006.

S. Bayar and A. Yurdakul, Dynamic Partial Self-Reconfiguration on Spartan-III FPGAs via a Parallel Configuration Access Port (PCAP), 2nd HiPEAC workshop on Reconfigurable Computing, 2008.

K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen et al., Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs, 2007 International Conference on Field Programmable Logic and Applications, pp.351-356, 2007.
DOI : 10.1109/FPL.2007.4380671

C. Claus, F. H. Muller, J. Zeppenfeld, and W. Stechele, A new framework to accelerate Virtex-II Pro dynamic partial selfreconfiguration, IPDPS, pp.1-7, 2007.

A. Cuoccio, P. R. Grassi, V. Rana, M. D. Santambrogio, and D. Sciuto, A Generation Flow for Self-Reconfiguration Controllers Customization, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), pp.279-284, 2008.
DOI : 10.1109/DELTA.2008.35

R. Koch, T. Pionteck, C. Albrecht, and E. Maehle, An adaptive system-on-chip for network applications, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006.
DOI : 10.1109/IPDPS.2006.1639445

O. Labbani, J. Dekeyser, P. Boulet-andéand´andé, and . Rutten, Introducing control in the gaspard2 data-parallel metamodel: Synchronous approach, Proceedings of the International Workshop MARTES: Modeling and Analysis of Real-Time and Embedded Systems, 2005.
URL : https://hal.archives-ouvertes.fr/inria-00000911

A. Gamatié, E. Rutten, and H. Yu, A Model for the Mixed-Design of Data-Intensive and Control-Oriented Embedded Systems, INRIA, 2008.

R. B. Atitallah, E. Piel, S. Niar, P. Marquet, and J. Dekeyser, Multilevel MPSOC simulation using an MDE approach, 2007 IEEE International SOC Conference, 2007.
DOI : 10.1109/SOCC.2007.4545457

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.160.9401

J. Dekeyser, A. Gamatié, S. Meftali, and I. Quadri, Models for Co-Design of Hetero-geneous Dynamic Multiprocessor SoCs, Book Chapter Heterogeneous Embedded Systems: Design Theory and Practice, 2010.