The number of integrated transistors that can be contained on a chip are increasing at an exponential rate, along with rise in targeted sophisticated applications. Thus the design of Systems-on-Chip (SoC) is becoming more and more complex. Hence there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. This paper presents a novel approach for expressing system adaptivity and reconfigurability in Gaspard, a SoC co-design framework, with special focus on partially dynamically reconfigurable FPGAs. The framework is compliant with UML MARTE profile proposed by Object Management Group, for modeling and analysis of realtime embedded systems. The overall objective is to carry out system modeling at a high abstraction level expressed in UML; and afterwards, transform these high level models into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis