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Integrating Mode Automata Control Models in SoC Co-Design for Dynamically Reconfigurable FPGAs

Imran Rafiq Quadri 1, 2, * Samy Meftali 1, 2 Jean-Luc Dekeyser 1, 2 
* Corresponding author
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : The number of integrated transistors that can be contained on a chip are increasing at an exponential rate, along with rise in targeted sophisticated applications. Thus the design of Systems-on-Chip (SoC) is becoming more and more complex. Hence there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. This paper presents a novel approach for expressing system adaptivity and reconfigurability in Gaspard, a SoC co-design framework, with special focus on partially dynamically reconfigurable FPGAs. The framework is compliant with UML MARTE profile proposed by Object Management Group, for modeling and analysis of realtime embedded systems. The overall objective is to carry out system modeling at a high abstraction level expressed in UML; and afterwards, transform these high level models into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis
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Submitted on : Thursday, May 27, 2010 - 11:28:13 AM
Last modification on : Friday, February 4, 2022 - 3:16:30 AM
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  • HAL Id : inria-00486919, version 1


Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. Integrating Mode Automata Control Models in SoC Co-Design for Dynamically Reconfigurable FPGAs. International Conference on Design and Architectures for Signal and Image Processing (DASIP 09), Sep 2009, Nice, France. ⟨inria-00486919⟩



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