P. Lysaght, B. Blodget, and J. Mason, Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs, 2006 International Conference on Field Programmable Logic and Applications, 2006.
DOI : 10.1109/FPL.2006.311188

B. Blodget, S. Mcmillan, and P. Lysaght, A lightweight approach for embedded reconfiguration of FPGAs, 2003 Design, Automation and Test in Europe Conference and Exhibition, 2003.
DOI : 10.1109/DATE.2003.1253642

I. Dart, GASPARD SoC Framework, 2009.

A. Gamatié, A model driven design framework for high performance embedded systems, 2008.

F. Maraninchi and Y. Rémond, Mode-automata: About modes and states for reactive systems, European Symposium On Programming. Lisbon (Portugal), 1998.
DOI : 10.1007/BFb0053571

O. Labbani, Introducing control in the gaspard2 data-parallel metamodel: Synchronous approach, Proceedings of the International Workshop MARTES: Modeling and Analysis of Real-Time and Embedded Systems, 2005.
URL : https://hal.archives-ouvertes.fr/inria-00000911

A. Gamatié, H. Rutten, and . Yu, A Model for the Mixed-Design of Data-Intensive and Control-Oriented Embedded Systems, INRIA, 2008.

H. Yu, U. /. Lifl, and F. , A MARTE-Based Reactive Model for Data-Parallel Intensive Processing: Transformation toward the Synchronous Model, 2008.

Y. Atat and N. Zergainoh, Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), pp.9-14, 2007.
DOI : 10.1109/ISVLSI.2007.90

URL : https://hal.archives-ouvertes.fr/hal-00265119

G. Gailliard, Transaction Level Modelling of SCA Compliant Software Defined Radio Waveforms and Platforms PIM/PSM, 2007 Design, Automation & Test in Europe Conference & Exhibition, 2007.
DOI : 10.1109/DATE.2007.364418

URL : https://hal.archives-ouvertes.fr/hal-00524695

S. Mohanty, Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation, LCTES/Scopes, 2002.

A. Koudri, Using MARTE in the MOPCOM SoC/SoPC Co- Methodology, MARTE Workshop at DATE'08, 2008.

F. Berthelot, F. Nouvel, and D. Houzet, A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs, EURASIP Journal on Embedded Systems, vol.49, issue.3, pp.1-18, 2008.
DOI : 10.1155/S1110865704402066

URL : https://hal.archives-ouvertes.fr/hal-00320192

M. Boden, GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs, 2008 IEEE Computer Society Annual Symposium on VLSI, 2008.
DOI : 10.1109/ISVLSI.2008.21

R. Damasevicius and V. Stuikys, Application of UML for hardware design based on design process model, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), 2004.
DOI : 10.1109/ASPDAC.2004.1337574

W. Mcumber and B. Cheng, UML-based analysis of embedded systems using a mapping to VHDL, Proceedings 4th IEEE International Symposium on High-Assurance Systems Engineering, pp.56-63, 1999.
DOI : 10.1109/HASE.1999.809475

P. Sedcole, Modular partial reconfiguration in virtex FPGAs, International Conference on Field Programmable Logic and Applications, 2005., pp.211-216, 2005.
DOI : 10.1109/FPL.2005.1515724

J. Becker, M. Huebner, and M. Ullmann, Real-Time Dynamically Run-Time Reconfigurations for Power/Cost-optimized Virtex FPGA Realizations, VLSI'03, 2003.

M. Huebner, New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.
DOI : 10.1109/ISVLSI.2006.67

C. Schuck, A framework for dynamic 2D placement on FPGAs, 2008 IEEE International Symposium on Parallel and Distributed Processing, 2008.
DOI : 10.1109/IPDPS.2008.4536512

. Xilinx, Early Access Partial Reconfigurable Flow, 2006.

S. Bayar and A. , Dynamic Partial Self-Reconfiguration on Spartan-III FPGAs via a Parallel Configuration Access Port (PCAP), HiPEAC'08 Workshop on Reconfigurable Computing, 2008.

C. Claus, A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration, 2007 IEEE International Parallel and Distributed Processing Symposium, pp.1-7, 2007.
DOI : 10.1109/IPDPS.2007.370362

A. Cuoccio, A Generation Flow for Self-Reconfiguration Controllers Customization, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), pp.279-284, 2008.
DOI : 10.1109/DELTA.2008.35

R. Koch, An adaptive system-on-chip for network applications, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006.
DOI : 10.1109/IPDPS.2006.1639445

I. Quadri, S. Meftali, and J. Dekeyser, A model driven design flow for fpgas supporting partial reconfiguration Tentative publication date, International Journal of Reconfigurable Computing, 2009.

P. Boulet, Array-OL revisited, multidimensional intensive signal processing specification, 2007.
URL : https://hal.archives-ouvertes.fr/inria-00128840