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Power and Performance Aware Reconfigurable Cache for CMPs

Abstract : This paper investigates the problem of partitioning a shared cache among threads executing in a Chip Multi-Processor (CMP). We propose Reconfigurable Cache for CMPs (ReCaC), a low-overhead run-time mechanism that dynamically partitions the cache based on the phase behavior of threads. Unlike the previously proposed per- formance aware partitioning approaches, ReCaC targets to use a minimum number of ways to trade-off between power and perfor- mance. ReCaC dynamically reverts back to a performance centric cache partitioning scheme if the power savings are not achievable. Our results show that in a 2-core architecture ReCaC saves on av- erage 51.5% power in a L2 cache, which corresponds to 11.5% power savings of the processor chip and the memory. The overall processor energy efficiency is improved by up to 13.6%, achieving on average 8.5%. ReCaC proves to be scalable, saving on average 10.8% and 12.5% of the processor chip and memory power in 4- and 8-core architectures, respectively.
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https://hal.inria.fr/inria-00492854
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Submitted on : Thursday, June 17, 2010 - 11:53:52 AM
Last modification on : Wednesday, November 29, 2017 - 9:51:20 AM

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  • HAL Id : inria-00492854, version 1

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Kamil Kedzierski, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero. Power and Performance Aware Reconfigurable Cache for CMPs. IFMT'10 - Second International Forum on Next Generation Multicore/Manycore Technologies, Jun 2010, Saint Malo, France. ⟨inria-00492854⟩

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