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An Adaptive Cache Coherence Protocol for Chip Multiprocessors

Abstract : Multi-core architectures also referred to as Chip Multiprocessors (CMPs) have emerged as the dominant architecture for both desktop and high-performance systems. CMPs introduce many challenges that need to be addressed to achieve the best performance. One of the big challenges comes with the shared-memory model observed in such architectures which is the cache coherence overhead problem. Contemporary architectures employ write-invalidate based protocols which are known to generate coherence misses that yield to latency issues. On the other hand, write-update based protocols can solve the coherence misses problem but they tend to generate excessive network traffic which is especially not desirable for CMPs. Previous studies have shown that a single protocol approach is not sufficient for many sharing patterns. As a solution, this paper evaluates an adaptive protocol which targets write-update optimizations for producer-consumer sharing patterns. This work targets a minimalistic hardware extension approach to test the bene ts of such adaptive protocols in a practical environment. Experimental study is conducted on a 16-core CMP by using a full-system simulator with selected scientic applications from SPLASH-2 and NAS parallel benchmark suites. Results show up to 40% improvement for coherence misses which corresponds to 15% application speedup.
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Submitted on : Thursday, June 17, 2010 - 12:26:26 PM
Last modification on : Thursday, April 15, 2021 - 6:04:01 PM


  • HAL Id : inria-00492862, version 1



Abdullah Kayi, Tarek El-Ghazawi. An Adaptive Cache Coherence Protocol for Chip Multiprocessors. IFMT'10 - Second International Forum on Next Generation Multicore/Manycore Technologies, Jun 2010, Saint Malo, France. ⟨inria-00492862⟩



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