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Guarded Power Gating in a Multi-Core Setting

Abstract : Power gating is an increasingly important actuation knob in chip-level dynamic power management. In a multi-core setting, a key design issue in this context, is determining the right balance of gating at the unit-level (within a core) and at the core-level. Another issue is how to architect the predictive control associated with such gating, in order to ensure maximal power savings at minimal performance loss. We use an abstract, analytical modeling framework to understand and discuss the fundamental tradeoffs in such a design. We consider plausible ranges of software/hardware control latencies and workload characteristics to understand when and where it makes sense to disable one or both of the gating mechanisms (i.e. intra- and inter-core). The overall goal of this research is to devise predictive power gating algorithms in a multi-core setting, with built-in “guard” mechanisms to prevent negative outcomes: e.g. a net increase in power consumption or an unacceptable level of performance loss.
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https://hal.inria.fr/inria-00492866
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Submitted on : Thursday, June 17, 2010 - 1:00:10 PM
Last modification on : Sunday, December 17, 2017 - 7:04:03 AM
Long-term archiving on: : Monday, September 20, 2010 - 5:22:03 PM

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  • HAL Id : inria-00492866, version 1

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Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram. Guarded Power Gating in a Multi-Core Setting. WEED 2010 - Workshop on Energy-Efficient Design, Jun 2010, Saint Malo, France. ⟨inria-00492866⟩

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