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Dynamic Power Redistribution in Failure Prone CMPs

Abstract : Future chip multiprocessors (CMPs) will be capable of deconfiguring faulty units in order to permit continued operation in the presence of wear-out failures. However, the unforeseen downside is pipeline imbalance due to other portions of the pipeline now being overprovisioned with respect to the deconfigured functionality. We propose PowerTransfer, a novel CMP architecture that dynamically redistributes the chip power under pipeline imbalances that arise from deconfiguring faulty units. Through rebalancing – achieved by temporary, symbiotic deconfiguration of additional functionality within the degraded core – power is harnessed for use elsewhere on the chip. This additional power is dynamically transferred to portions of the multi-core chip that can realize a performance boost from turning on previously dormant microarchitectural features. We demonstrate that a realistic PowerTransfer manager achieves chip-wide performance improvements of up to 25% compared to architectures that simply deconfigure faulty units without regard to the resulting inefficiency.
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https://hal.inria.fr/inria-00492867
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Submitted on : Thursday, June 17, 2010 - 1:10:58 PM
Last modification on : Friday, June 11, 2021 - 5:12:08 PM
Long-term archiving on: : Monday, September 20, 2010 - 4:56:20 PM

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  • HAL Id : inria-00492867, version 1

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Paula Petrica, Jonathan A. Winter, David H. Albonesi. Dynamic Power Redistribution in Failure Prone CMPs. WEED 2010 - Workshop on Energy-Efficient Design, Jun 2010, Saint Malo, France. ⟨inria-00492867⟩

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