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Using Partial Tag Comparison in LowPower Snoopbased Chip Multiprocessors

Abstract : In this work we introduce power optimizations relying on partial tag comparison (PTC) in snoop‐based chip multiprocessors. Our optimizations rely on the observation that detecting tag mismatches in a snoopbased chip multiprocessor does not require aggressively processing the entire tag. In fact, a high percentage of cache mismatches could be detected by utilizing a small subset but highly informative portion of the tag bits. Based on this, we introduce a source‐based snoop filtering mechanism referred to as S‐PTC. In S‐PTC possible remote tag mismatches are detected prior to sending the request. We reduce power as S‐PTC prevents sending unnecessary snoops and avoids unessential tag lookups at the endpoints. Furthermore, S‐PTC improves performance as a result of early cache miss detection. S‐PTC improves average performance from 2.9 % to 3.5% for different configurations and for the SPLASH‐2 benchmarks used in this study. Our solutions reduce snoop request bandwidth from 78.5% to 81.9% and average tag array dynamic power by about 52%.
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https://hal.inria.fr/inria-00492875
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Submitted on : Thursday, June 17, 2010 - 1:27:41 PM
Last modification on : Wednesday, June 23, 2021 - 3:10:01 PM
Long-term archiving on: : Monday, September 20, 2010 - 5:22:28 PM

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Ali Shafiee, Narges Shahidi, Amirali Baniasadi. Using Partial Tag Comparison in LowPower Snoopbased Chip Multiprocessors. WEED 2010 - Workshop on Energy-Efficient Design, Jun 2010, Saint Malo, France. ⟨inria-00492875⟩

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