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Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks

Abstract : The world needs special-purpose accelerators to meet future constraints on computation and power consumption. Choosing appropriate accelerator architectures is a key challenge. In this work, we present a pintool designed to help evaluate the potential benefit of accelerating a particular function. Our tool gathers cross-procedural data usage patterns, including implicit dependencies not captured by arguments and return values. We then use this data to characterize the limits of hardware procedural acceleration imposed by on-chip communication and storage systems. Through an understanding the bottlenecks in future accelerator-based systems we will focus future research on the most performance-critical regions of the design. Accelerator designers will also find our tool useful for selecting which regions of their application to accelerate.
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https://hal.inria.fr/inria-00492929
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Submitted on : Thursday, June 17, 2010 - 2:23:15 PM
Last modification on : Friday, December 18, 2020 - 6:46:05 PM
Long-term archiving on: : Monday, October 22, 2012 - 11:55:46 AM

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  • HAL Id : inria-00492929, version 1

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Marta Kim, Stephen A. Edwards. Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks. AMAS-BT - 3rd Workshop on Architectural and Microarchitectural Support for Binary Translation, Jun 2010, Saint Malo, France. ⟨inria-00492929⟩

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