Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks

Abstract : The world needs special-purpose accelerators to meet future constraints on computation and power consumption. Choosing appropriate accelerator architectures is a key challenge. In this work, we present a pintool designed to help evaluate the potential benefit of accelerating a particular function. Our tool gathers cross-procedural data usage patterns, including implicit dependencies not captured by arguments and return values. We then use this data to characterize the limits of hardware procedural acceleration imposed by on-chip communication and storage systems. Through an understanding the bottlenecks in future accelerator-based systems we will focus future research on the most performance-critical regions of the design. Accelerator designers will also find our tool useful for selecting which regions of their application to accelerate.
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Communication dans un congrès
Mauricio Breternitz and Robert Cohn and Erik Altman and Youfeng Wu. AMAS-BT - 3rd Workshop on Architectural and Microarchitectural Support for Binary Translation, Jun 2010, Saint Malo, France. 2010
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Marta Kim, Stephen A. Edwards. Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks. Mauricio Breternitz and Robert Cohn and Erik Altman and Youfeng Wu. AMAS-BT - 3rd Workshop on Architectural and Microarchitectural Support for Binary Translation, Jun 2010, Saint Malo, France. 2010. 〈inria-00492929〉

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