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IOMMU: Strategies for Mitigating the IOTLB Bottleneck

Abstract : The input/output memory management unit (IOMMU) was recently introduced into mainstream computer architecture when both Intel and AMD added IOMMUs to their chip-sets. An IOMMU provides memory protection from I/O devices by enabling system software to control which areas of physical memory an I/O device may access. However, this protection incurs additional direct memory access (DMA) overhead due to the required address resolution and validation. IOMMUs include an input/output translation lookaside buffer (IOTLB) to speed-up address resolution, but still every IOTLB cache-miss causes a substantial increase in DMA latency and performance degradation of DMA-intensive workloads. In this paper we first demonstrate the potential negative impact of IOTLB cachemisses on workload performance. We then propose both system software and hardware enhancements to reduce IOTLB miss rate and accelerate address resolution. These enhancements can lead to a reduction of over 60% in IOTLB miss-rate for common I/O intensive workloads.
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https://hal.inria.fr/inria-00493752
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Submitted on : Monday, June 21, 2010 - 11:51:27 AM
Last modification on : Thursday, January 6, 2022 - 2:50:02 PM
Long-term archiving on: : Wednesday, September 22, 2010 - 6:01:51 PM

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  • HAL Id : inria-00493752, version 1

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Nadav Amit, Muli Ben-yehuda, Ben-Ami yassour. IOMMU: Strategies for Mitigating the IOTLB Bottleneck. WIOSCA 2010 - Sixth Annual Workshorp on the Interaction between Operating Systems and Computer Architecture, Jun 2010, Saint Malo, France. ⟨inria-00493752⟩

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