Managing Wire Delay in Large Chip-Multiprocessor Caches, 37th International Symposium on Microarchitecture (MICRO-37'04), pp.319-330, 2004. ,
DOI : 10.1109/MICRO.2004.21
Survey of code-size reduction methods, ACM Computing Surveys, vol.35, issue.3, 2003. ,
DOI : 10.1145/937503.937504
Multi-execution: multicore caching for data-similar executions, ISCA, 2009. ,
First the tick, now the tock: Intel microarchitecture (nehalem). Intel Corporation ,
Optimizing Replication, Communication, and Capacity Allocation in CMPs, ACM SIGARCH Computer Architecture News, vol.33, issue.2, pp.357-368, 2005. ,
DOI : 10.1145/1080695.1070001
Enhanced Code Compression for Embedded RISC Processors, Proceedings of PLDI, 1999. ,
Compiler techniques for code compaction, ACM Transactions on Programming Languages and Systems, vol.22, issue.2, 2000. ,
DOI : 10.1145/349214.349233
The anatomy of the grid -enabling scalable virtual organizations, International Journal of Supercomputer Applications, vol.15, 2001. ,
Improving instruction cache performance in OLTP, ACM Transactions on Database Systems, vol.31, issue.3, pp.887-920, 2006. ,
DOI : 10.1145/1166074.1166079
CATCH, Proceedings of the conference on Design, automation and test in Europe, DATE '08, 2008. ,
DOI : 10.1145/1403375.1403720
Hyperthreading technology in the netburst microarchitecture, IEEE Micro, vol.23, issue.2, pp.56-65, 2003. ,
DOI : 10.1109/MM.2003.1196115
Improving code density using compression techniques, Proceedings of 30th Annual International Symposium on Microarchitecture, pp.194-203, 1997. ,
DOI : 10.1109/MICRO.1997.645810
The glite workload management system, 4th International Conference on Grid and Pervasive Computing, 2009. ,
DLL-conscious instruction fetch optimization for SMT processors, Journal of Systems Architecture, vol.54, issue.12, pp.1089-1100, 2008. ,
DOI : 10.1016/j.sysarc.2008.04.014
The microarchitecture of the pentium 4 processor, Intel Technology Journal, 2001. ,
Amazon elastic compute cloud: User guide, 2009. ,
Ultrasparc t2: A highly-threaded, power-efficient, sparc soc, 2007. ,
Dynamically configurable shared CMP helper engines for improved performance, ACM SIGARCH Computer Architecture News, vol.33, issue.4, pp.70-79, 2005. ,
DOI : 10.1145/1105734.1105744
Automatically characterizing large scale program behavior, ASPLOS, 2002. ,
POWER7 multi-core processor design, Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Micro-42, 2009. ,
DOI : 10.1145/1669112.1669114
Cache Memories, ACM Computing Surveys, vol.14, issue.3, pp.473-530, 1982. ,
DOI : 10.1145/356887.356892
Symbiotic jobscheduling for a simultaneous multithreaded processor, ACM SIGARCH Computer Architecture News, vol.28, issue.5, pp.234-244, 2000. ,
DOI : 10.1145/378995.379244
Simultaneous Multithreading: Maximizing On-Chip Parallelism, 22nd Annual International Symposium on Computer Architecture, 1995. ,
Simulation and modeling of a simultaneous multithreading processor, Int. CMG Conference, 1996. ,
Performance estimation of multistreamed, superscalar processors, Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences HICSS-94, 1994. ,
DOI : 10.1109/HICSS.1994.323172