Cycle-Accurate 64+-Core FPGA-Based Hybrid Simulator

Abstract : Nowadays, computer architecture researches mainly focus on the multicore hardware and software design. As compared with the traditional uniprocessor counterpart, the system complexity of multicore simulators is dramatically augmented, which is spurred by the increase in core number. Full-system fidelity, fast simulation speed, and cycle-level accuracy are the essential requirements of the advanced multicore simulator adopted as the research vehicle for studying and evaluating multicore systems. Tsinghua Emulation Accelerator of Multicore System or TEAMS is an FPGA accelerated cycle-accurate hybrid simulation platform with full-system fidelity. By leveraging state-of-the-art Xilinx Virtex 5 Field Programmable Gate Arrays (FPGAs) and the high volume on board SRAMand DRAM, the most concerned issues in multicore microprocessor research, i.e., Cache with data coherency and network on chip (NoC), are emulated and accelerated by hardware in our simulator. Therefore, developers can achieve the precise performance evaluations, which include the hardware cost, the power consumption and the process efficiency, of Cache and NoC in their designs. On the other hand, the functional simulation of each core is executed by the software simulator, which makes the proposed simulator suitable for a wide variety of instruction set processors. By using hardwaresoftware and inter-FPGA synchronizing techniques, the proposed platform realizes the 64-processor cycle-accurate simulation with one FPGA rack. Together, the proposed techniques also enable the outstanding scalability. Without an overwhelming effort, our simulator can perform the 512-core simulation with four FPGA racks.
Type de document :
Communication dans un congrès
Omar Hammami and Sandra Larrabee. WARP - 5th Annual Workshop on Architectural Research Prototyping, Jun 2010, Saint Malo, France. 2010
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Soumis le : mardi 22 juin 2010 - 10:45:41
Dernière modification le : lundi 20 juin 2016 - 14:10:32
Document(s) archivé(s) le : vendredi 24 septembre 2010 - 17:41:24


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  • HAL Id : inria-00494130, version 1



G.X. Liu, G.H. Li, P. Gao, H. Qu, Z.Y. Liu, et al.. Cycle-Accurate 64+-Core FPGA-Based Hybrid Simulator. Omar Hammami and Sandra Larrabee. WARP - 5th Annual Workshop on Architectural Research Prototyping, Jun 2010, Saint Malo, France. 2010. 〈inria-00494130〉



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