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Performance Estimation for the Exploration of CPU-Accelerator Architectures

Abstract : In this paper we present an approach for studying the design space when interfacing reconfigurable accelerators with a CPU. For this purpose we introduce a framework based on the LLVM infrastructure that performs hardware/software partitioning with runtime estimation utilizing profiling information and code analysis. We apply it to reconfigurable accelerators that are controlled by a CPU via a direct low-latency interface but also have direct access to the memory hierarchy. Our results show that a shared L2 cache for CPU and accelerator seems to be the most promising design point for a range of applications.
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Submitted on : Tuesday, June 22, 2010 - 11:22:51 AM
Last modification on : Thursday, July 26, 2018 - 3:20:10 PM
Long-term archiving on: : Friday, September 24, 2010 - 5:17:56 PM


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  • HAL Id : inria-00494171, version 1



Tobias Kenter, Marco Platzner, Christian Plessl, Michael Kauschke. Performance Estimation for the Exploration of CPU-Accelerator Architectures. WARP - 5th Annual Workshop on Architectural Research Prototyping, Jun 2010, Saint Malo, France. ⟨inria-00494171⟩



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