Performance Estimation for the Exploration of CPU-Accelerator Architectures
Résumé
In this paper we present an approach for studying the design space when interfacing reconfigurable accelerators with a CPU. For this purpose we introduce a framework based on the LLVM infrastructure that performs hardware/software partitioning with runtime estimation utilizing profiling information and code analysis. We apply it to reconfigurable accelerators that are controlled by a CPU via a direct low-latency interface but also have direct access to the memory hierarchy. Our results show that a shared L2 cache for CPU and accelerator seems to be the most promising design point for a range of applications.
Domaines
Architectures Matérielles [cs.AR]
Origine : Fichiers produits par l'(les) auteur(s)
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