Automatic Embedded Multicore Generation and Evaluation Methodology: a Case Study of a NOC Based 2400-cores on Very Large Scale Emulator

Abstract : Future generation embedded multicore will be based on hundreds of processors connected through Network on Chip (NOC) . Design productivity of embedded multicore is a major challenge for the semiconductor industry. In this paper, an automatic very large scale NoC design methodology based on FPGA IP is proposed to accelerate the embedded multicore design productivity using very large scale multi-FPGA platform emulation. The large scale multiprocessor is divided into pieces of FPGA IP. Local NoC is designed for each FPGA IP. Then a top level NoC connects all the local NoCs together to form the large scale multiprocessor. In this paper we extend our previous work to reach 2400-cores NoC based multiprocessor which is generated using this methodology within 3 days.
Type de document :
Communication dans un congrès
Omar Hammami and Sandra Larrabee. WARP - 5th Annual Workshop on Architectural Research Prototyping, Jun 2010, Saint Malo, France. 2010
Liste complète des métadonnées

Littérature citée [15 références]  Voir  Masquer  Télécharger

https://hal.inria.fr/inria-00494176
Contributeur : Ist Rennes <>
Soumis le : mardi 22 juin 2010 - 11:34:12
Dernière modification le : mercredi 29 novembre 2017 - 15:52:35
Document(s) archivé(s) le : vendredi 24 septembre 2010 - 17:43:13

Fichier

WARP10-hammami-ENSTA.pdf
Fichiers produits par l'(les) auteur(s)

Identifiants

  • HAL Id : inria-00494176, version 1

Collections

Citation

Omar Hammami, X. Li, L. Burgun, S. Delerse. Automatic Embedded Multicore Generation and Evaluation Methodology: a Case Study of a NOC Based 2400-cores on Very Large Scale Emulator. Omar Hammami and Sandra Larrabee. WARP - 5th Annual Workshop on Architectural Research Prototyping, Jun 2010, Saint Malo, France. 2010. 〈inria-00494176〉

Partager

Métriques

Consultations de la notice

142

Téléchargements de fichiers

271