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Automatic Embedded Multicore Generation and Evaluation Methodology: a Case Study of a NOC Based 2400-cores on Very Large Scale Emulator

Abstract : Future generation embedded multicore will be based on hundreds of processors connected through Network on Chip (NOC) . Design productivity of embedded multicore is a major challenge for the semiconductor industry. In this paper, an automatic very large scale NoC design methodology based on FPGA IP is proposed to accelerate the embedded multicore design productivity using very large scale multi-FPGA platform emulation. The large scale multiprocessor is divided into pieces of FPGA IP. Local NoC is designed for each FPGA IP. Then a top level NoC connects all the local NoCs together to form the large scale multiprocessor. In this paper we extend our previous work to reach 2400-cores NoC based multiprocessor which is generated using this methodology within 3 days.
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https://hal.inria.fr/inria-00494176
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Submitted on : Tuesday, June 22, 2010 - 11:34:12 AM
Last modification on : Wednesday, May 11, 2022 - 12:06:06 PM
Long-term archiving on: : Friday, September 24, 2010 - 5:43:13 PM

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Omar Hammami, X. Li, L. Burgun, S. Delerse. Automatic Embedded Multicore Generation and Evaluation Methodology: a Case Study of a NOC Based 2400-cores on Very Large Scale Emulator. WARP - 5th Annual Workshop on Architectural Research Prototyping, Jun 2010, Saint Malo, France. ⟨inria-00494176⟩

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