A. A. Jerraya and W. Wolf, Multiprocessor Systems-on-Chips, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00012749

J. H. Kelm, D. R. Johnson, M. R. Johnson, N. C. Crago, W. Tuohy et al., An Architecture and Scalable Programming Interface for a 1000-core Accelerator, International Symposium on Computer Architecture (ISCA'09), 2009.

J. Wawrzynek, D. Patterson, M. Oskin, C. Shin-lien-lu-;-kozyrakis, J. C. Hoe et al., RAMP: Research Accelerator for Multiple Processors, IEEE Micro, vol.27, issue.2, pp.46-57, 2007.
DOI : 10.1109/MM.2007.39

X. Li and O. Hammami, NOCDEX: Network on Chip Design Space Exploration Through Direct Execution and Options Selection Through Principal Component Analysis, 2006 International Symposium on Industrial Embedded Systems, pp.1-4, 2006.
DOI : 10.1109/IES.2006.357469

R. , B. Mouhoub, and O. Hammami, MOCDEX: Multiprocessor on Chip Multiobjective Design Space Exploration with Direct Execution, EURASIP Journal on Embedded Systems, vol.2006, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00847913

O. Hammami, Heterogeneous multiprocessor on chip compiler, architecture, place and route design space exploration, MELECON 2008, The 14th IEEE Mediterranean Electrotechnical Conference, 2008.
DOI : 10.1109/MELCON.2008.4618468

N. Genko, D. Atienza, G. De-micheli, J. M. Mendias, R. Hermida et al., A Complete Network-On-Chip Emulation Framework, Design, Automation and Test in Europe, p.5, 2005.
DOI : 10.1109/DATE.2005.5
URL : https://hal.archives-ouvertes.fr/hal-00181642

M. D. Nava, P. Blouet, P. Teninge, M. Coppola, T. Ben-ismail et al., An open platform for developing multiprocessor SoCs, Computer, vol.38, issue.7, pp.60-67, 2005.
DOI : 10.1109/MC.2005.218

E. S. Chung, E. Nurvitadhi, J. C. Hoe, B. Falsafi, and K. , Mai Virtualized Full- System Emulation of Multiprocessors using FPGAs, 2007.

K. Asonvic, RAMP: Research Accelerator for Multiprocessors, 2nd Workshop on Architectural Research Prototyping, p.2006

S. A. Arteris and . Http, arteris.com [14] NoC Solution 1.10, NoC Compiler user's Guide, o918v2rs4 Arteris www.arteris.com [15] Danube 1.10 ? Packet Transport Units Technical reference ? 04277v3rs6, 2008.

E. Team-zebu-xxl, Emulation platform. www.eve-team.com [18] X.Li and O.Hammami, An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography, International Journal of Reconfigurable Computing, vol.2009, p.631490, 2009.

X. Li and O. Hammami, BB-762: Design and Implementation of 762 Processor Multiprocessor and OCP-IP Benchmarking, 2009.

O. Hammami, X. Li, L. Larzul, and L. Burgun, Automatic Design Methodologies for Large Scale MPSOC and Prototyping on Multi- FPGA Platforms, ISOCC) 2009, invited talk [21] EEMBC, MultiBench? 1.0 Multicore Benchmark Software

C. Bienia and K. Li, PARSEC 2.0: A New Benchmark Suite for Chip- Multiprocessors, Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation, 2009.