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FaulTM: Fault-Tolerance Using Hardware Transactional Memory

Abstract : Fault-tolerance has become an essential concern for processor designers due to increasing soft-error rates. In this study, we are motivated by the fact that Transactional Memory (TM) hardware provides an ideal base upon which to build a fault-tolerant system. We show how it is possible to provide low-cost faulttolerance for serial programs by using a minimallymodified Hardware Transactional Memory (HTM) that features lazy conflict detection, lazy data versioning. This scheme, called FaulTM, employs a hybrid hardware-software fault-tolerance technique. On the software side, FaulTM programming model is able to provide the flexibility for programmers to decide between performance and reliability. Our experimental results indicate that FaulTM produces relatively less performance overhead by reducing the number of comparisons and by leveraging already proposed TM hardware. We also conduct experiments which indicate that the baseline FaulTM design has a good error coverage. To the best of our knowledge, this is the first architectural fault-tolerance proposal using Hardware Transactional Memory.
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Submitted on : Tuesday, June 22, 2010 - 3:51:57 PM
Last modification on : Wednesday, November 29, 2017 - 9:51:20 AM
Long-term archiving on: : Friday, September 24, 2010 - 5:49:31 PM


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  • HAL Id : inria-00494285, version 1



Gulay Yalcin, Osman Unsal, Ibrahim Hur, Adrian Cristal, Mateo Valero. FaulTM: Fault-Tolerance Using Hardware Transactional Memory. Pespma 2010 - Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture, Jun 2010, Saint Malo, France. ⟨inria-00494285⟩



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