M. Advanced and . Devices, AMD Athlon X2 Dual-Core Details, 2007.

C. J. Beckmann and C. D. Polychronopoulos, Fast barrier synchronization hardware, Proceedings SUPERCOMPUTING '90, pp.180-189, 1990.
DOI : 10.1109/SUPERC.1990.130019

M. Budiu and S. C. Goldstein, Fast compilation for pipelined reconfigurable fabrics, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays , FPGA '99, pp.195-205, 1999.
DOI : 10.1145/296399.296459
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.21.5677

C. Ca¸scavalca¸scaval, J. Castaños, L. Ceze, M. Denneau, M. Gupta et al., Evaluation of a Multithreaded Architecture for Cellular Computing, Proc. 8th IEEE Symposium on High Performance Computer Architecture, pp.311-321, 2002.

T. Callahan, J. Hauser, and J. Wawrzynek, The Garp architecture and C compiler, Computer, vol.33, issue.4, pp.62-69, 2000.
DOI : 10.1109/2.839323

J. Carrillo and P. Chow, The effect of reconfigurable units in superscalar processors, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays , FPGA '01, pp.141-150, 2001.
DOI : 10.1145/360276.360328

E. Caspi, M. Chu, R. Huang, J. Yeh, J. Wawrzynek et al., Stream Computations Organized for Reconfigurable Execution (SCORE), Proceedings of the 10th Int'l Workshop on Field-Programmable Logic and Applications, pp.605-614, 2000.
DOI : 10.1007/3-540-44614-1_65

M. Dales, Managing a reconfigurable processor in a general purpose workstation environment, 2003 Design, Automation and Test in Europe Conference and Exhibition, pp.980-985, 2003.
DOI : 10.1109/DATE.2003.1253732

M. Feldman, FPGA Acceleration Gets a Boost from HP, Intel. HPCWire, 2007.

M. Feldman, Reconfigurable Computing Prospects on the Rise, HPCWire, 2008.

P. Garcia and K. Compton, A Reconfigurable Hardware Interface for a Modern Computing System, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007), pp.73-84, 2007.
DOI : 10.1109/FCCM.2007.49

M. I. Gordon, W. Thies, M. Karczmarek, J. Lin, A. S. Meli et al., A Stream Compiler for Communication-Exposed Architectures, Proc. 10th ACM Symposium on Architectural Support for Programming Languages and Operating Systems, pp.291-303, 2002.

S. W. Keckler, W. J. Dally, D. Maskit, N. P. Carter, A. Chang et al., Exploiting Fine-Grain Thread Level Parallelism on the MIT Multi-ALU Processor, Proc. 25th IEEE/ACM Int'l Symposium on Computer Architecture, pp.306-317, 1998.

G. Ottoni, R. Rangan, A. Stoler, and D. August, Automatic Thread Extraction with Decoupled Software Pipelining, 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05), pp.105-118, 2005.
DOI : 10.1109/MICRO.2005.13
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.131.4010

E. Raman, G. Ottoni, A. Raman, M. J. Bridges, and D. I. August, Parallel-stage decoupled software pipelining, Proceedings of the sixth annual IEEE/ACM international symposium on Code generation and optimization , CGO '08, pp.114-123, 2008.
DOI : 10.1145/1356058.1356074
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.118.8168

R. Rangan, N. Vachharajani, A. Stoler, G. Ottoni, D. August et al., Support for High-Frequency Streaming in CMPs, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), pp.259-272, 2006.
DOI : 10.1109/MICRO.2006.47

R. Rangan, N. Vachharajani, M. Vachharajani, and D. August, Decoupled software pipelining with the synchronization array, Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004., pp.177-188, 2004.
DOI : 10.1109/PACT.2004.1342552

J. Sampson, R. Gonzalez, J. Collard, N. P. Jouppi, M. Schlansker et al., Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), pp.235-246, 2006.
DOI : 10.1109/MICRO.2006.23

. Sesc-architectural and . Simulator, http://sourceforge.net/projects/sesc, 2007.

S. Shang and K. Hwang, Distributed hardwired barrier synchronization for scalable multiprocessor clusters, IEEE Transactions on Parallel and Distributed Systems, vol.6, issue.6, pp.591-605, 1995.
DOI : 10.1109/71.388040

W. Thies, M. Karczmarek, and S. P. Amarasinghe, StreamIt: A Language for Streaming Applications, CC '02: Proceedings of the 11th International Conference on Compiler Construction, pp.179-196, 2002.
DOI : 10.1007/3-540-45937-5_14

N. Vachharajani, R. Rangan, E. Raman, M. J. Bridges, G. Ottoni et al., Speculative Decoupled Software Pipelining, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), pp.49-59, 2007.
DOI : 10.1109/PACT.2007.4336199
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.73.9040

M. Watkins, M. Cianchetti, and D. Albonesi, Shared reconfigurable architectures for CMPS, 2008 International Conference on Field Programmable Logic and Applications, 2008.
DOI : 10.1109/FPL.2008.4629948
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.568.4653

Z. A. Ye, N. Shenoy, and P. Banerjee, A C compiler for a processor with a reconfigurable functional unit, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays , FPGA '00, pp.95-100, 2000.
DOI : 10.1145/329166.329187