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Design Trade-offs for Memory Level Parallelism on an Asymmetric Multicore System

Abstract : Asymmetric Multicore Processors (AMP) offer a unique opportunity to integrate many kinds of cores together with each core optimized for different uses. However, the impact of techniques for exploiting high Memory Level Parallelism (MLP) on core specialization and selection on AMPs has not been investigated. Extracting high memory-level parallelism is essential to tolerate long memory latencies, and such techniques are critical for speeding up singlethreaded codes which are memory bound. In this work, we explored multiple core configurations with different widths and frequencies and concluded that a narrow faster core is better than a wide slower core for regions of high MLP. We use an effective hardware-level scheduling mechanism, which requires identifying MLP phases on the fly and scheduling execution on the appropriate core. We successfully exploit the custom MLP core during clustered L2 misses and otherwise use the wider issue core. Compared to a single-core design optimized for both modes of operation, our AMP design provides a geometric mean performance improvement of 4% and 10% for SPECint and SPECfp, respectively, with a maximum speedup of 19.5%. For the same study, it achieves a 10% and 25% energy delay2 reduction fo SPECint and SPECfp, respectively.
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Submitted on : Tuesday, June 22, 2010 - 3:56:05 PM
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  • HAL Id : inria-00494292, version 1



George Patsilaras, Niket K. Choudhary, James Tuck. Design Trade-offs for Memory Level Parallelism on an Asymmetric Multicore System. Pespma 2010 - Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture, Jun 2010, Saint Malo, France. ⟨inria-00494292⟩



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