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The Time Model of Logical Clocks available in the OMG MARTE profile

Charles André 1 Julien Deantoni 1 Frédéric Mallet 1 Robert de Simone 1
1 AOSTE - Models and methods of analysis and optimization for systems with real-time and embedding constraints
CRISAM - Inria Sophia Antipolis - Méditerranée , Inria Paris-Rocquencourt, Laboratoire I3S - COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués
Abstract : Multiform logical time, introduced and made popular through its central role in Synchronous Language theory, is already present in many formalisms pertaining to embedded system design, although usually in a hidden fashion. Logical time considers time bases that can be generated from any sort of sequences of events, not necessarily equally spaced in physical time. Our main goal here is to capture some of the essence of multiform logical time, and encapsulate it into a dedicated syntax (CCSL, Clock Constraint Specification Language, part of the UML profile for MARTE). CCSL provides ways to express loose or strict constraints between distinct logical clocks. Solving such clock constraints amounts to relating clocks to a common reference one, which then can be thought of as closer to physical. We motivate the role of MARTE Time Model and CCSL by using them to explain and formally characterize important semantic features of East-ADL2/AUTOSar, AADL, and Ptolemy's SDF models.
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https://hal.inria.fr/inria-00495664
Contributor : Frédéric Mallet <>
Submitted on : Monday, June 28, 2010 - 2:43:50 PM
Last modification on : Tuesday, May 26, 2020 - 6:50:21 PM

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  • HAL Id : inria-00495664, version 1

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Charles André, Julien Deantoni, Frédéric Mallet, Robert de Simone. The Time Model of Logical Clocks available in the OMG MARTE profile. Sandeep K. Shukla and Jean-Pierre Talpin. Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, Springer Science+Business Media, LLC 2010, pp.28, 2010, 978-1-4419-6399-4. ⟨inria-00495664⟩

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