Polychronous Analysis of Timing Constraints in UML MARTE

Huafeng Yu 1 Jean-Pierre Talpin 1 Loïc Besnard 1 Thierry Gautier 1 Frédéric Mallet 2 Charles André 2 Robert De Simone 2
1 ESPRESSO - Synchronous programming for the trusted component-based engineering of embedded systems and mission-critical systems
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
2 AOSTE - Models and methods of analysis and optimization for systems with real-time and embedding constraints
CRISAM - Inria Sophia Antipolis - Méditerranée , Inria Paris-Rocquencourt, Laboratoire I3S - COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués
Abstract : The UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) defines a broadly expressive Time Model to provide a generic timed interpretation for UML models. As a part of MARTE, Clock Constraint Specification Language (CCSL) allows the specification of systems with multiple clock domains as well as nondeterminism. In this paper, we propose to take advantage of Polychrony clock calculus, named hierarchization, to analyze timed systems specified in CCSL, and to generate code for simulation considering determinism. Hierarchization enables to identify the endochrony property in a system that allows code generation ensuring determinism. The presented work is being integrated into the TimeSquare environment dedicated to the simulation of MARTE timed systems.
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Communication dans un congrès
IEEE International Workshop on Model-Based Engineering for Real-Time Embedded Systems Design, May 2010, Parador of Carmona, Spain. 7 p., 2010
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Huafeng Yu, Jean-Pierre Talpin, Loïc Besnard, Thierry Gautier, Frédéric Mallet, et al.. Polychronous Analysis of Timing Constraints in UML MARTE. IEEE International Workshop on Model-Based Engineering for Real-Time Embedded Systems Design, May 2010, Parador of Carmona, Spain. 7 p., 2010. 〈inria-00497249〉

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