A low-area yet performant FPGA implementation of Shabal

Jérémie Detrey 1, * Pierrick Gaudry 1 Karim Khalfallah 2
* Auteur correspondant
1 CARAMEL - Cryptology, Arithmetic: Hardware and Software
Inria Nancy - Grand Est, LORIA - ALGO - Department of Algorithms, Computation, Image and Geometry
Abstract : In this paper, we present an efficient FPGA implementation of the SHA-3 hash function candidate Shabal. Targeted at the recent Xilinx Virtex-5 FPGA family, our design achieves a relatively high throughput of 2 Gbit/s at a cost of only 153 slices, yielding a throughput-vs.-area ratio of 13.4 Mbit/s per slice. Our work can also be ported to Xilinx Spartan-3 FPGAs, on which it supports a throughput of 800 Mbit/s for only 499 slices, or equivalently 1.6 Mbit/s per slice. According to the SHA-3 Zoo website, this work is among the smallest reported FPGA implementations of SHA-3 candidates, and ranks first in terms of throughput per area.
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Communication dans un congrès
Alex Biryukov and Guang Gong and Douglas Stinson. 17th International Workshop on Selected Areas in Cryptography, SAC 2010, Aug 2010, Waterloo, Canada. Springer, 6544, pp.99-113, 2011, Lecture Notes in Computer Science. 〈10.1007/978-3-642-19574-7_7〉
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Jérémie Detrey, Pierrick Gaudry, Karim Khalfallah. A low-area yet performant FPGA implementation of Shabal. Alex Biryukov and Guang Gong and Douglas Stinson. 17th International Workshop on Selected Areas in Cryptography, SAC 2010, Aug 2010, Waterloo, Canada. Springer, 6544, pp.99-113, 2011, Lecture Notes in Computer Science. 〈10.1007/978-3-642-19574-7_7〉. 〈inria-00498705〉

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