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Accelerating HMMER on FPGA using Parallel Prefixes and Reductions

Abstract : HMMER is a widely used tool in bioinformatics, based on Profile Hidden Markov Models. The computation kernels of HMMER i.e. MSV and P7Viterbi are very compute intensive and data dependencies restrict to sequential execution. In this paper, we propose an original parallelization scheme for HMMER by rewriting their mathematical formulation, to expose the hidden potential parallelization opportunities. Our parallelization scheme targets FPGA technology, and our architecture can achieve 10 times speedup compared with that of latest HMMER3 SSE version, while not compromising on sensitivity of original algorithm.
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https://hal.inria.fr/inria-00515298
Contributor : Naeem Abbas <>
Submitted on : Friday, December 17, 2010 - 10:04:09 AM
Last modification on : Friday, July 10, 2020 - 4:06:59 PM
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  • HAL Id : inria-00515298, version 2

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Naeem Abbas, Steven Derrien, Sanjay Rajopadhye, Patrice Quinton. Accelerating HMMER on FPGA using Parallel Prefixes and Reductions. [Research Report] RR-7370, INRIA. 2010. ⟨inria-00515298v2⟩

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