Data-Aware Task Scheduling on Multi-Accelerator based Platforms

Cédric Augonnet 1, 2 Jérôme Clet-Ortega 1, 2 Samuel Thibault 1, 2 Raymond Namyst 1, 2
2 RUNTIME - Efficient runtime systems for parallel architectures
Inria Bordeaux - Sud-Ouest, CNRS - Centre National de la Recherche Scientifique : UMR5800, UB - Université de Bordeaux
Abstract : To fully tap into the potential of heterogeneous machines composed of multicore processors and multiple accelerators, simple offloading approaches in which the main trunk of the application runs on regular cores while only specific parts are offloaded on accelerators are not sufficient. The real challenge is to build systems where the application would permanently spread across the entire machine, that is, where parallel tasks would be dynamically scheduled over the full set of available processing units. To face this challenge, we previously proposed StarPU, a runtime system capable of scheduling tasks over multicore machines equipped with GPU accelerators. StarPU uses a software virtual shared memory (VSM) that provides a high-level programming interface and automates data transfers between processing units so as to enable a dynamic scheduling of tasks. We now present how we have extended StarPU to minimize the cost of transfers between processing units in order to efficiently cope with multi-GPU hardware configurations. To this end, our runtime system implements data prefetching based on asynchronous data transfers, and uses data transfer cost prediction to influence the decisions taken by the task scheduler. We demonstrate the relevance of our approach by benchmarking two parallel numerical algorithms using our runtime system. We obtain significant speedups and high efficiency over multicore machines equipped with multiple accelerators. We also evaluate the behaviour of these applications over clusters featuring multiple GPUs per node, showing how our runtime system can combine with MPI.
Type de document :
Communication dans un congrès
16th International Conference on Parallel and Distributed Systems, Dec 2010, Shangai, China. 2010
Contributeur : Cédric Augonnet <>
Soumis le : mercredi 6 octobre 2010 - 16:00:29
Dernière modification le : mercredi 9 septembre 2015 - 16:34:21
Document(s) archivé(s) le : jeudi 25 octobre 2012 - 16:35:23


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  • HAL Id : inria-00523937, version 1



Cédric Augonnet, Jérôme Clet-Ortega, Samuel Thibault, Raymond Namyst. Data-Aware Task Scheduling on Multi-Accelerator based Platforms. 16th International Conference on Parallel and Distributed Systems, Dec 2010, Shangai, China. 2010. <inria-00523937>



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