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Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation

Imran Rafiq Quadri 1 Samy Meftali 1, 2 Jean-Luc Dekeyser 1, 2
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : Due to continuous hardware/software evolution related to Systems-on-Chip (SoC) and the addition of features such as Partial Dynamic Reconfiguration, the complexity of SoC design and development has escalated exponentially. This has resulted in increased time to market and development costs. Without the usage of effective design tools and methodologies, large complex SoCs are becoming increasingly difficult to manage, resulting in a productivity gap. The design space, representing all technical decisions that need to be elaborated by the SoC design team is therefore, becoming immense and difficult to explore. Similarly, manipulation of these systems at low implementation levels such as Register Transfer Level (RTL) can be hindered by human interventions and the subsequent errors. This paper presents a novel design methodology that decreases the design complexity by raising the design abstraction levels. It makes use of Model- Driven Engineering and the UML MARTE profile to move from high level UML models to automatic code generation, for implementing dynamically reconfigurable SoCs
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Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation. Conference on Design and Architectures for Signal and Image Processing (DASIP 2010), Oct 2010, Edinburgh, United Kingdom. ⟨inria-00525003⟩

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