Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs, 2006 International Conference on Field Programmable Logic and Applications, 2006. ,
DOI : 10.1109/FPL.2006.311188
Model transformation: the heart and soul of model-driven software development, IEEE Software, vol.20, issue.5, pp.42-45, 2003. ,
DOI : 10.1109/MS.2003.1231150
A Model-Driven Design Framework for Massively Parallel Embedded Systems, ACM Transactions on Embedded Computing Systems, vol.10, issue.4, p.2010 ,
DOI : 10.1145/2043662.2043663
MARTE based model driven design methodology for targeting dynamically reconfigurable FPGA based SoCs, 2010. ,
URL : https://hal.archives-ouvertes.fr/tel-00486483
Using MARTE in the MOPCOM SoC/SoPC Co- Methodology, MARTE Workshop at DATE'08, 2008. ,
A co-design approach for embedded system modeling and code generation with UML and MARTE, 2009 Design, Automation & Test in Europe Conference & Exhibition, 2009. ,
DOI : 10.1109/DATE.2009.5090662
URL : https://hal.archives-ouvertes.fr/hal-00369036
A model driven design flow for fpgas supporting partial reconfiguration, International Journal of Reconfigurable Computing, 2009. ,
MARTE based design flow for Partially Reconfigurable Systems-on-Chips, 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 09), 2009. ,
URL : https://hal.archives-ouvertes.fr/inria-00486846
High-level model of dynamically reconfigurable architectures, Conference on Design and Architectures for Signal and Image Processing, pp.1-7, 2009. ,
URL : https://hal.archives-ouvertes.fr/inria-00446951
Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), pp.35-40, 2007. ,
DOI : 10.1109/ISVLSI.2007.69
Handel-C Implementation of Early-Access Partial-Reconfiguration for Software Defined Radio, 2008 IEEE Wireless Communications and Networking Conference, pp.1103-1108, 2008. ,
DOI : 10.1109/WCNC.2008.199
A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs, EURASIP Journal on Embedded Systems, vol.49, issue.3, pp.1-18, 2008. ,
DOI : 10.1155/S1110865704402066
URL : https://hal.archives-ouvertes.fr/hal-00320192
SPARK: a high-level synthesis framework for applying parallelizing compiler transformations, 16th International Conference on VLSI Design, 2003. Proceedings., p.461, 2003. ,
DOI : 10.1109/ICVD.2003.1183177
High-level synthesis under I/O Timing and Memory constraints, 2005 IEEE International Symposium on Circuits and Systems, pp.680-683, 2005. ,
DOI : 10.1109/ISCAS.2005.1464679
URL : https://hal.archives-ouvertes.fr/hal-00077297
Integrating Mode Automata Control Models in SoC Co-Design for Dynamically Reconfigurable FPGAs, International Conference on Design and Architectures for Signal and Image Processing, 2009. ,
URL : https://hal.archives-ouvertes.fr/inria-00486919
Synchronous Modeling and Analysis of Data Intensive Applications, EURASIP Journal on Embedded Systems, vol.2008, issue.1, 2008. ,
DOI : 10.1007/BF01379404
A MARTE based reactive model for data-parallel intensive processing: Transformation toward the synchronous model, 2008. ,
ISE Foundation Software, 2009. ,
Mode-Automata: a new domain-specific construct for the development of safe critical systems, Science of Computer Programming, vol.46, issue.3, pp.219-254, 2003. ,
DOI : 10.1016/S0167-6423(02)00093-X
A lightweight approach for embedded reconfiguration of FPGAs, 2003 Design, Automation and Test in Europe Conference and Exhibition, p.3, 2003. ,
DOI : 10.1109/DATE.2003.1253642
Heterogeneous Embedded Systems -Design Theory and Practice, High-level modeling of dynamically reconfigurable heterogeneous systems, 2010. ,
Uml 2 infrastructure (final adopted specifcation), 2007. ,
Model based design flow for implementing an anti-collision radar detection system, 2009 9th International Conference on Intelligent Transport Systems Telecommunications, (ITST), 2009. ,
DOI : 10.1109/ITST.2009.5399285
URL : https://hal.archives-ouvertes.fr/inria-00525006