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Modeling reconfigurable Systems-on-Chips with UML MARTE profile: an exploratory analysis

Sana Cherif 1 Imran Rafiq Quadri 1, * Samy Meftali 1, 2 Jean-Luc Dekeyser 1, 2 
* Corresponding author
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible nature. However due to the tremendous amount of hardware resources available in these systems, new design methodologies and tools are required to reduce their design complexity. In this paper we present an exploratory analysis for specification of these systems, while utilizing the UML MARTE (Modeling and Analysis of Real-time and Embedded Systems) profile. Our contributions permit us to model fine grain reconfigurable FPGA based SoC architectures while extending the profile to integrate new features such as Partial Dynamic Reconfiguration supported by these modern systems. Finally we present the current limitations of the MARTE profile and ask some open questions regarding how these high level models can be effectively used as input for commercial FPGA simulation and synthesis tools. Solutions to these questions can help in creating a design flow from high level models to synthesis, placement and execution of these reconfigurable SoCs.
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Submitted on : Sunday, October 10, 2010 - 6:44:08 PM
Last modification on : Friday, February 4, 2022 - 3:17:55 AM
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  • HAL Id : inria-00525004, version 1


Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. Modeling reconfigurable Systems-on-Chips with UML MARTE profile: an exploratory analysis. 13th Euromicro Conference on Digital System Design (DSD 2010), Sep 2010, Lille, France. ⟨inria-00525004⟩



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