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MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs

Imran Rafiq Quadri 1 Samy Meftali 1, 2 Jean-Luc Dekeyser 1, 2 
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology is utilized to model fine grain reconfigurable architectures such as FPGAs and extends the standard to integrate new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The goal is to carry out modeling at a high abstraction level expressed in UML (Unified Modeling Language) and following transformations of these models, automatically generate the code necessary for FPGA implementation.
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Submitted on : Sunday, October 10, 2010 - 6:58:46 PM
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  • HAL Id : inria-00525007, version 1


Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs. Sixth IEEE Workshop on Embedded Systems for Real-time Multimedia (ESTIMedia 2008), Oct 2008, Atlanta, United States. ⟨inria-00525007⟩



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