Targeting Reconfigurable FPGA based SoCs using the MARTE UML profile: from high abstraction levels to code generation

Imran Rafiq Quadri 1 Huafeng Yu 2 Abdoulaye Gamatié 1, 3 Samy Meftali 1, 3 Jean-Luc Dekeyser 1, 3 Éric Rutten 4
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
2 ESPRESSO - Synchronous programming for the trusted component-based engineering of embedded systems and mission-critical systems
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
3 LIFL - Laboratoire d'Informatique Fondamentale de Lille
4 SARDES - System architecture for reflective distributed computing environments
Inria Grenoble - Rhône-Alpes, LIG - Laboratoire d'Informatique de Grenoble
Abstract : As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools to handle SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach to address system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC codesign framework: Gaspard. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented work is based on Model-Driven Engineering and the UML MARTE profile proposed by Object Management Group, for modeling and analysis of real-time embedded systems. The paper thus presents a complete design flow to move from high level MARTE models to code generation, for implementation of dynamically reconfigurable SoCs.
Type de document :
Article dans une revue
International Journal of Embedded Systems, Inderscience, 2010, 18 p
Liste complète des métadonnées

https://hal.inria.fr/inria-00525015
Contributeur : Mister Dart <>
Soumis le : mercredi 10 novembre 2010 - 12:45:09
Dernière modification le : vendredi 13 janvier 2017 - 14:18:04
Document(s) archivé(s) le : vendredi 11 février 2011 - 02:58:30

Fichier

ijes09.pdf
Fichiers produits par l'(les) auteur(s)

Identifiants

  • HAL Id : inria-00525015, version 2

Collections

INRIA | LIG | IRISA | LIFL | UGA | UNIV-LILLE3 | IRISA-D4 | LIG_SRCPR | UR1-UFR-ISTIC

Citation

Imran Rafiq Quadri, Huafeng Yu, Abdoulaye Gamatié, Samy Meftali, Jean-Luc Dekeyser, et al.. Targeting Reconfigurable FPGA based SoCs using the MARTE UML profile: from high abstraction levels to code generation. International Journal of Embedded Systems, Inderscience, 2010, 18 p. <inria-00525015v2>

Exporter

BibTeX TEI DC DCterms EndNote

Partager

Métriques

Consultations de
la notice

375

Téléchargements du document

354

Contact


archive-ouverte@inria.fr