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Targeting Reconfigurable FPGA based SoCs using the MARTE UML profile: from high abstraction levels to code generation
Abstract : As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools to handle SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach to address system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC codesign framework: Gaspard. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented work is based on Model-Driven Engineering and the UML MARTE profile proposed by Object Management Group, for modeling and analysis of real-time embedded systems. The paper thus presents a complete design flow to move from high level MARTE models to code generation, for implementation of dynamically reconfigurable SoCs.
Cited literature [40 references]
https://hal.inria.fr/inria-00525015
Contributor : Mister Dart <>
Submitted on : Wednesday, November 10, 2010 - 12:45:09 PM
Last modification on : Thursday, November 19, 2020 - 1:00:24 PM
Long-term archiving on: : Friday, February 11, 2011 - 2:58:30 AM
Contributor : Mister Dart <>
Submitted on : Wednesday, November 10, 2010 - 12:45:09 PM
Last modification on : Thursday, November 19, 2020 - 1:00:24 PM
Long-term archiving on: : Friday, February 11, 2011 - 2:58:30 AM
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ijes09.pdf
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