V. Aranega, J. Mottu, A. Etien, and J. Dekeyser, Traceability Mechanism for Error Localization in Model Transformations, 4th International Conference on Software and Data Technologies, 2009.

R. B. Atitallah, E. Piel, S. Niar, P. Marquet, and J. Dekeyser, Multilevel MPSoC simulation using an MDE approach, in 'SoCC, 2007.

S. Bayar and A. Yurdakul, Dynamic Partial Self- Reconfiguration on Spartan-III FPGAs via a Parallel Configuration Access Port (PCAP), in 'HiPEAC'08 Workshop on Reconfigurable Computing, 2008.

J. Becker, M. Huebner, and M. Ullmann, Real-Time Dynamically Run-Time Reconfigurations for Power/Costoptimized Virtex FPGA Realizations, in 'VLSI'03, 2003.

N. Bergmann, J. Williams, and P. Waldeck, Egret: A flexible platform for real-time reconfigurable system-on-chip, Proceedings of International Conference on Engineering Reconfigurable Systems and Algorithms', pp.300-303, 2003.

B. Blodget, S. Mcmillan, and P. Lysaght, A lightweight approach for embedded reconfiguration of FPGAs, in 'Design, Automation & Test in Europe, p.3, 2003.

P. Boulet, Array-OL revisited, multidimensional intensive signal processing specification, 2007.
URL : https://hal.archives-ouvertes.fr/inria-00128840

P. Boulet, Formal Semantics of Array-OL, a Domain Specific Language for Intensive Multidimensional Signal Processing, 2008.
URL : https://hal.archives-ouvertes.fr/inria-00261178

A. Brito, M. Kuhnle, M. Hubner, J. Becker, and E. Melcher, Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), pp.35-40, 2007.
DOI : 10.1109/ISVLSI.2007.69

C. Claus, F. Muller, J. Zeppenfeld, and W. Stechele, A new framework to accelerate Virtex-II Pro dynamic partial selfreconfiguration, IPDPS, pp.1-7, 2007.

L. Douadi, P. Deloof, and Y. Elhillali, Real time implementation of reconfigurable correlation radar for road anticollision system, 2008 IEEE International Conference on Industrial Technology, pp.1-7, 2008.
DOI : 10.1109/ICIT.2008.4608551

C. Ebeling, D. Cronquist, and P. Franklin, RaPiD ??? Reconfigurable pipelined datapath, Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers (FPL' 96, pp.126-135, 1996.
DOI : 10.1007/3-540-61730-2_13

F. Berthelot, F. Nouvel, and D. Houzet, A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs, EURASIP Journal on Embedded Systems, vol.49, issue.3, pp.1-18, 2008.
DOI : 10.1155/S1110865704402066

URL : https://hal.archives-ouvertes.fr/hal-00320192

M. Faugere, T. Bourbeau, R. Simone, and G. Sebastien, MARTE: Also an UML Profile for Modeling AADL Applications, 12th IEEE International Conference on Engineering Complex Computer Systems (ICECCS 2007), pp.359-364, 2007.
DOI : 10.1109/ICECCS.2007.29

A. Gamatié, L. Beux, S. Piel, E. , B. Atitallah et al., A Model-Driven Design Framework for Massively Parallel Embedded Systems, ACM Transactions on Embedded Computing Systems, vol.10, issue.4, 2010.
DOI : 10.1145/2043662.2043663

A. Gamatié, E. Rutten, and H. Yu, A Model for the Mixed- Design of Data-Intensive and Control-Oriented Embedded Systems, 2008.

A. Gamatié, E. Rutten, H. Yu, P. Boulet, and J. Dekeyser, Synchronous Modeling and Analysis of Data Intensive Applications', EURASIP Journal on Embedded Systems, 2008.

D. Harel, Statecharts: a visual formalism for complex systems, Science of Computer Programming, vol.8, issue.3, pp.231-274, 1987.
DOI : 10.1016/0167-6423(87)90035-9

J. P. Diguet, G. Gogniat, and J. Philippe, EPICURE: A partitioning and co-design framework for reconfigurable computing, Microprocessors and Microsystems, vol.30, issue.6, pp.367-387, 2006.
DOI : 10.1016/j.micpro.2006.02.015

URL : https://hal.archives-ouvertes.fr/hal-00089393

R. Koch, T. Pionteck, C. Albrecht, and E. Maehle, An adaptive system-on-chip for network applications, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006.
DOI : 10.1109/IPDPS.2006.1639445

O. Labbani, J. Dekeyser, P. Boulet, and E. Rutten, Introducing control in the Gaspard2 Data-Parallel MetaModel: Synchronous Approach, Proceedings of the International Workshop MARTES: Modeling and Analysis of Real-Time and Embedded Systems, 2005.
URL : https://hal.archives-ouvertes.fr/inria-00000911

D. Latella, I. Majzik, and M. Massink, Automatic Verification of a Behavioral Subset of UML Statechart Diagrams Using the SPIN Model-Checker, in 'Formal Aspects Computing, pp.637-664, 1999.

L. Beux and S. , Un flot de conception pour applications de traitement du signal systématique implémentées sur FPGAà FPGA`FPGAà base d'Ingénierie Dirigée par les Modèles, 2007.

P. Lysaght, B. Blodget, and J. Mason, Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs, 2006 International Conference on Field Programmable Logic and Applications, 2006.
DOI : 10.1109/FPL.2006.311188

F. Maraninchi and Y. Rémond, Mode-Automata: a new domain-specific construct for the development of safe critical systems, Science of Computer Programming, vol.46, issue.3, pp.219-254, 2003.
DOI : 10.1016/S0167-6423(02)00093-X

G. Moore, Cramming more components into integrated circuits, pp.114-117, 1965.

B. Nascimento, P. Sérgio, M. Maciel, P. Romero, M. Lima et al., A partial reconfigurable architecture for controllers based on Petri nets, Proceedings of the 17th symposium on Integrated circuits and system design , SBCCI '04, pp.16-21, 2004.
DOI : 10.1145/1016568.1016581

K. G. Nezami, P. W. Stephens, and S. D. Walker, Handel-C Implementation of Early-Access Partial-Reconfiguration for Software Defined Radio, 2008 IEEE Wireless Communications and Networking Conference, pp.1103-1108, 2008.
DOI : 10.1109/WCNC.2008.199

E. M. Panainte, K. Bertels, and S. Vassiliadis, The Molen compiler for reconfigurable processors, ACM Transactions on Embedded Computing Systems, vol.6, issue.1, 2007.
DOI : 10.1145/1210268.1210274

K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen et al., Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self- Reconfiguration on Xilinx Spartan III FPGA', FPL, pp.351-356, 2007.

I. R. Quadri, P. Boulet, S. Meftali, and J. Dekeyser, Using an MDE Approach for Modeling of Interconnection Networks, 2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008), 2008.
DOI : 10.1109/I-SPAN.2008.40

URL : https://hal.archives-ouvertes.fr/inria-00565155

I. R. Quadri, Y. Elhillali, S. Meftali, and J. Dekeyser, Model based design flow for implementing an anti-collision radar detection system, 2009 9th International Conference on Intelligent Transport Systems Telecommunications, (ITST), 2009.
DOI : 10.1109/ITST.2009.5399285

URL : https://hal.archives-ouvertes.fr/inria-00525006

I. Quadri, S. Meftali, and J. Dekeyser, A Model Driven design flow for FPGAs supporting Partial Reconfiguration, International Journal of Reconfigurable Computing, 2009.

I. R. Quadri, S. Meftali, and J. Dekeyser, Integrating Mode Automata Control Models in SoC Co-Design for Dynamically Reconfigurable FPGAs, International Conference on Design and Architectures for Signal and Image Processing (DASIP 09), 2009.
URL : https://hal.archives-ouvertes.fr/inria-00486919

S. Sendall and W. Kozaczynski, Model transformation: the heart and soul of model-driven software development, IEEE Software, vol.20, issue.5, pp.42-45, 2003.
DOI : 10.1109/MS.2003.1231150

B. Salefski and L. Caglar, Reconfigurable computing in wireless, Proceedings of the 38th annual Design Automation Conference (DAC'01)', ACM, pp.178-183, 2001.

C. Schuck, M. Kuhnle, M. Hubner, and J. Becker, A framework for dynamic 2D placement on FPGAs, 2008 IEEE International Symposium on Parallel and Distributed Processing, 2008.
DOI : 10.1109/IPDPS.2008.4536512

A. Tumeo, M. Monchiero, G. Palermo, F. Ferrandi, and D. Sciuto, A Self-Reconfigurable Implementation of the JPEG Encoder', ASAP, pp.24-29, 2007.

J. Vidal, F. D. Lamotte, and G. Gogniat, A co-design approach for embedded system modeling and code generation with UML and MARTE, 2009 Design, Automation & Test in Europe Conference & Exhibition, 2009.
DOI : 10.1109/DATE.2009.5090662

URL : https://hal.archives-ouvertes.fr/hal-00369036

H. /. Yu and F. Lifl, A MARTE-Based Reactive Model for Data-Parallel Intensive Processing: Transformation toward the Synchronous Model URL: http://sites.google.com/siteSafe Design of High-Performance Embedded Systems in a MDE framework, Innovations in Systems and Software Engineering, pp.215-222, 2008.