Y. Atat and N. Zergainoh, Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), pp.9-14, 2007.
DOI : 10.1109/ISVLSI.2007.90

URL : https://hal.archives-ouvertes.fr/hal-00265119

. Atitallah, Multilevel MPSOC simulation using an MDE approach, 2007 IEEE International SOC Conference, 2007.
DOI : 10.1109/SOCC.2007.4545457

L. Benini and G. Micheli, Networks on chips: a new SoC paradigm, Computer, vol.35, issue.1, 2001.
DOI : 10.1109/2.976921

. Berthelot, A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs, EURASIP Journal on Embedded Systems, vol.49, issue.3, pp.1-18, 2008.
DOI : 10.1155/S1110865704402066

URL : https://hal.archives-ouvertes.fr/hal-00320192

. Boden, GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs, 2008 IEEE Computer Society Annual Symposium on VLSI, 2008.
DOI : 10.1109/ISVLSI.2008.21

P. Boulet, Array-OL Revisited, Multidimensional Intensive Signal Processing Specification, 2007.
URL : https://hal.archives-ouvertes.fr/inria-00128840

. Carver, Relocation and Automatic Floor-planning of FPGA Partial Configuration Bit- Streams, Tech. rep, 2008.

. Cesario, Component-Based Design Approach for Multicore SoCs. Design Automatic Conference, p.789, 2002.
URL : https://hal.archives-ouvertes.fr/hal-00008062

. Dally, Not Wires: On-Chip Interconnection Networks, IEEE Proc. Design Automation Conf, pp.684-689, 2001.
DOI : 10.1109/dac.2001.935594

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1.5322

R. Damasevicius and V. Stuikys, Application of UML for hardware design based on design process model, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), 2004.
DOI : 10.1109/ASPDAC.2004.1337574

. Dart, GASPARD SoC Framework, 2009.

. Dorairaj, PlanAhead Software as a Platform for Partial Reconfiguration, Xcell Journal, vol.55, pp.68-71, 2005.

. Eclipse, Eclipse Modeling Framework

. Eclipse, Eclipse Modeling Framework Technology

. Gailliard, Transaction Level Modelling of SCA Compliant Software Defined Radio Waveforms and Platforms PIM/PSM, 2007 Design, Automation & Test in Europe Conference & Exhibition, p.7, 2007.
DOI : 10.1109/DATE.2007.364418

URL : https://hal.archives-ouvertes.fr/hal-00524695

. Gamatié, A model driven design framework for high performance embedded systems, 2008.

. Guo, Optimized generation of data-path from C codes for fpgas, Design, Automation & Test in Europe, DATE'05, pp.112-117, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00181503

H. Zimmermann, OSI Reference Model--The ISO Model of Architecture for Open Systems Interconnection, IEEE Transactions on Communications, vol.28, issue.4, pp.425-432, 1980.
DOI : 10.1109/TCOM.1980.1094702

I. Panades and A. Greiner, Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures, First International Symposium on Networks-on-Chip (NOCS'07), pp.83-92, 2007.
DOI : 10.1109/NOCS.2007.14

. Kangmin, A 51 mW 1.6 GHz on-chip network for low-power heterogeneous SoC platform

. Koch, An adaptive system-on-chip for network applications, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006.
DOI : 10.1109/IPDPS.2006.1639445

. Koudri, Using MARTE in the MOPCOM SoC/SoPC Co-Methodology, MARTE Workshop at DATE'08, 2008.

K. Kim, An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip, Proc. IEEE Int. Symp. on Circuits and Systems, pp.2357-2360, 2005.

M. Kreutz, Energy and Latency Evaluation of NoC Topologies, 2005 IEEE International Symposium on Circuits and Systems, pp.5866-5869, 2005.
DOI : 10.1109/ISCAS.2005.1465973

. Lattard, A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pp.258-601, 2007.
DOI : 10.1109/ISSCC.2007.373392

J. Liebeherr and T. K. Beam, HyperCast: A Protocol for Maintaining Multicast Group Members in a Logical Hypercube Topology, Proceedings First International Workshop on Networked Group Communication (NGC '99), pp.72-89, 1999.
DOI : 10.1007/978-3-540-46703-8_5

. Mcumber, UML-based analysis of embedded systems using a mapping to VHDL, Proceedings 4th IEEE International Symposium on High-Assurance Systems Engineering, pp.56-63, 1999.
DOI : 10.1109/HASE.1999.809475

T. Mens, V. Gorp, and P. , A Taxonomy of Model Transformation, Proceedings of the International Workshop on Graph and Model Transformation, pp.125-142, 2005.
DOI : 10.1016/j.entcs.2005.10.021

. Mohanty, Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation, LCTES/Scopes, 2002.

S. Murali, SUNMAP, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.914-919, 2004.
DOI : 10.1145/996566.996809

M. Planet, Portal of the Model Driven Engineering Community, 2007.

. Quadri, A Model Driven design flow for FPGAs supporting Partial Reconfiguration, International Journal of Reconfigurable Computing, 2009.

E. Rijpkema, Trade offs in the design a router with both guaranteed and best-effort services for networks on chip, Europe Conference and Exhibition, pp.350-355, 2003.

S. Lee, An 800 MHz star-connected on-chip network for application to systems on a chip, IEEE Int. Solid-States Circuits Conf, Digest of Technical papers, pp.468-469, 2003.

S. Sendall and W. Kozaczynski, Model transformation: the heart and soul of model-driven software development, IEEE Software, vol.20, issue.5, pp.42-45, 2003.
DOI : 10.1109/MS.2003.1231150

P. Stevens, A Landscape of Bidirectional Model Transformations, Generative and Transformational Techniques in Software Engineering, p.7, 2007.
DOI : 10.1007/978-3-540-88643-3_10

. Vangal, On An 80-Tile 1.28TFLOPS Network-on-Chip in 65 nm CMOS, Digest of Technical Papers, IEEE Intl. Solid State Circuits Conference, pp.98-589, 2007.

H. Wang, A Technology-aware and Energy-oriented Topology Exploration for Onchip Networks, Proc. Conf. on Design Automation and Test in Europe, pp.1238-1243, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00181300