Speculatively Vectorized Bytecode

Erven Rohou 1 Sergei Dyshel 2 Dorit Nuzman 2 Ira Rosen 2 Kevin Williams 1 Albert Cohen 3 Ayal Zaks 2
1 ALF - Amdahl's Law is Forever
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
2 IBM Research [HAIFA]
3 ALCHEMY - Architectures, Languages and Compilers to Harness the End of Moore Years
LRI - Laboratoire de Recherche en Informatique, UP11 - Université Paris-Sud - Paris 11, Inria Saclay - Ile de France, CNRS - Centre National de la Recherche Scientifique : UMR8623
Abstract : Diversity is a confirmed trend of computing systems, which present a complex and moving target to software developers. Virtual machines and just-in-time compilers have been proposed to mitigate the complexity of these systems. They do so by offering a single and stable abstract machine model thereby hiding architectural details from programmers. SIMD capabilities are common among current and expected computing systems. Efficient exploitation of SIMD instructions has become crucial for the performance of many applications. Existing auto-vectorizers operate within traditional static optimizing compilers, and use details about the target architecture when generating SIMD instructions. Unfortunately, auto-vectorizers are currently too complex to be included in a constrained Just-In-Time (JIT) environment. In this paper we propose Vapor SIMD: a speculative approach for effective just-in-time vectorization. Vapor SIMD first applies complex ahead-of-time techniques to vectorize source code and produce bytecode of a standard portable format. Advanced JIT compilers can then quickly tailor this bytecode to exploit SIMD capabilities of appropriate platforms, yielding up to 14.7x and 11.8x speedups on x86 and PowerPC platforms (including JIT-compilation time). JIT compilers can also seamlessly revert to non-vector code, in the absence of SIMD capabilities or in the case of a third-party non-vectorizing JIT compiler, yielding 93% or more of the original performance.
Type de document :
Communication dans un congrès
International Conference on High-Performance and Embedded Architectures and Compilers, Jan 2011, Heraklion, Greece. ACM, 2011
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Dernière modification le : mercredi 16 mai 2018 - 11:23:28
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INRIA | IRISA | UMR8623 | IRISA-D3 | UR1-UFR-ISTIC | UNIV-RENNES

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Erven Rohou, Sergei Dyshel, Dorit Nuzman, Ira Rosen, Kevin Williams, et al.. Speculatively Vectorized Bytecode. International Conference on High-Performance and Embedded Architectures and Compilers, Jan 2011, Heraklion, Greece. ACM, 2011. 〈inria-00525139〉

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